The future of CAD libraries: will IPC-7351 be adopted globally? Take a look into the creation of a land pattern standard.
The CAD land pattern library is one of the most important but often overlooked aspects of the electronics industry. By applying industry standard requirements, designers can gain competitive advantage through the automation of processes, from design through assembly. Automation begins with PCB design, because every electronic component requires a solder land pattern for PCB layout. Solder patterns either meet all the industry standard requirements for the sole purpose of electronic product creation automation, or fail to meet the industry standard requirements and create electronic product creation chaos.If you do not follow standardization, some companies will gladly take your money to verify whether the land patterns you created are built correctly. But even if the component will fit the land pattern that you created, other factors like "zero component rotation" must be considered to automate the manufacturing process. Basically, you either standardize or you don't.
Numerous organizations had input into the creation of the new land pattern standard, IPC-7351. To date, the key players in developing a standard CAD library are as listed below:
EIA--Electronic Industries Alliance
EIAJ--Electronic Industries Association of Japan
IEC--International Electrotechnical Commission
iNEMI--International Electronics Manufacturing Initiative
IPC--Association Connecting Electronics Industries
JEDEC--Joint Electron Device Engineering Council
JEITA--Japan Electronics and Information Technology Industries Association
NIST--National Institute of Standards and Technology
Before electronics product development automation can exist, five basic standards must exist in the standard CAD library. IPC-7351 has clearly defined and documented these standards. They are:
Land Pattern Naming Convention
A standard land pattern naming convention should use the physical attributes of the component and be consistent throughout. The IPC-7351 Land Pattern Naming Convention was accepted by NIST and published as a world standard. TABLE 1 shows a sample for SMT SOICs.
Zero Component Orientation
Taking into consideration component manufacturers' packaging, all CAD land patterns should have a clearly specified Pin 1 location and identification (see FIGURE 1). IPC-7351 has adopted the EIAJ/ANSI 481C as the standard Pin 1 location for CAD library construction. The following list has also been approved by IEC as a world standard:
[FIGURE 1 OMITTED]
1. Chip capacitors, resistors and inductors (CAP, RES and IND)--Pin 1 (positive) on left.
2. Molded inductors, resistors and polarized capacitors (INDM, RESM, CAPMP)--Pin 1 (positive) on left.
3. Precision wire-wound inductors (INDP)--Pin 1 (positive) on left.
4. MELF resistors and diodes (DIOMELF)--Pin 1 (cathode) on left.
5. Aluminum electrolytic capacitors (CAPAE)--Pin 1 (positive) on left.
6. SOT devices (SOT23, SOT23-5, etc.)--Pin 1 upper left.
7. TO252 and TO263 (DPAK type) devices--Pin 1 upper left.
8. Small outline gullwing ICs (SOIC, SOP, TSOP, SSOP, TSSOP)--Pin 1 upper left.
9. Ceramic flat packs (CFP)--Pin 1 upper left.
10. Small outline J lead ICs (SOJ)--Pin 1 upper left.
11. Quad flat pack ICs (PQFP, SQFP)--Pin 1 upper left.
12. Ceramic quad flat packs (CQFP)--Pin 1 upper left.
13. Bumper quad flat pack ICs (BQFP)--Pin 1 top center.
14. Plastic leaded chip carriers (PLCC)--Pin 1 top center.
15. Leadless chip carriers (LCC)--Pin 1 top center.
16. Quad flat no-lead ICs (QFNS, QFNRV and QFNRH) --Pin 1 upper left.
17. Ball grid arrays (BGA)--Pin A1 upper left.
Solder Joint Analysis
Solder joint analysis (for toe, heel and side solder fillets) has often perplexed PCB designers because the spectrum of PCB design is too broad for a single standard. Cell phones, computer motherboards and jet engines all require the use of land patterns with various tolerances. IPC-7351 introduces a three-tier library concept to accommodate these three totally different electronic products. Each library tier has its own unique solder joint mathematical algorithm that is applied to the various SMT component lead forms.
Component data is represented by:
L = Lead span
S = Space between terminals
W = Lead width
Manufacturing allowances are:
C : Component
F = Fabrication
P = Placement assembly
Three land pattern geometry variations are supplied for each of the device families. Before adapting the minimum land pattern variations, the user should consider product qualification testing based on the conditions shown in TABLE 2.
Density level A: The maximum land protrusion. For low-density product applications, the maximum land pattern condition has been developed to accommodate wave or flow solder of leadless chip devices and leaded gullwing devices. The geometry furnished for these devices, as well as inward and J-formed lead contact device families, may provide a wider process window for reflow solder processes as well.
Density level B: Median (nominal) land protrusion. This level is useful for products with a moderate level of component density. The median land patterns furnished for all device families will provide a robust solder attachment condition for reflow solder processes and should provide a condition suitable for wave or fellow soldering of leadless chip and leaded gullwing type devices.
Density level C: Minimum land protrusion. The high component density typical of portable and handheld product applications may benefit from this minimum land pattern geometry variation. But the minimum land pattern geometry may not be suitable for all product categories. The use of classes of performance (1, 2 and 3) is combined with that of component density levels (A, B and C) in explaining the condition of an electronic assembly. As an example, combining the description as levels 1A, 3B or 2C, would indicate the different combinations of performance and component density to aid in understanding the environment and the manufacturing requirements of a particular assembly. See FIGURE 2.
[FIGURE 2 OMITTED]
Land Pattern Origin
The land pattern origin point (the center of rotation) should be located where the assembly pick and place machines pick the component out of a tray or a tape and reel. Usually this is the centroid or the "center of gravity" of the component. See FIGURE 3.
[FIGURE 3 OMITTED]
Placement Courtyard
The placement courtyard (manufacturing boundary) plays an important role in helping the PCB designer arrange the land patterns in a PCB design. The assembly process depends on the PCB designer allowing enough space between the components for potential rework or to create machine head clearance. Each of the three tiers has a distinct placement courtyard clearance. See FIGURE 4.
[FIGURE 4 OMITTED]
Other considerations can be implemented into a standard CAD library.
Surface Mount Padstack
The surface mount component padstack consists of a solder pad, soldermask and solder paste. We've already discussed the creation of the pad size. The soldermask and paste mask size are typically the same as the pad size.
Soldermask. We allow the PCB manufacturer to expand the soldermask size according to rule technology that the PCB designer used to design the PCB layout. If the design layout has a trace/space rule setting of 0.012" (0.3 mm), the manufacturer can expand the soldermask size larger than if the design layout had a trace/space rule of 0.004" (0.1 mm). In the past, PCB designers forbade PCB manufacturers from modifying their Gerber data. But with today's CAM technology, board manufacturers often have more advanced design rule checking features than our CAD tools do. It's OK to let the board manufacturer adjust the soldermask size to accommodate their manufacturing equipment and soldermask application technique. It's probably better that PCB designers let the manufacturers do their job instead of guessing what the manufacturer needs will be. Most important, all soldermask sizes should be created in the padstack 1:1 scale so that the manufacturer can globally oversize all pads with the same oversize. All soldermask sizes are in increments of .002" (0.05 mm).
Solder paste. We allow the stencil maker to oversize the solder paste to match the specifications of the assembly shop that the paste mask stencil is made for. It is important that the solder paste size in the padstack is the same size as the pad to make the stencil creation process easy. If we make adjustments for BGA pad sizes or other SMT components, the stencil maker does not know this. It's much better to tell the solder paste stencil maker that all pad size data is 1:1 scale to the solder paste data.
Through-hole Mount Padstack
The through-hole padstack is much more complex than the surface mount padstack because it contains a drill size that goes all the way through the PCB. Parts of a typical through-hole padstack include:
* Top soldermask
* Top pad
* Inner laver pad
* Plane anti-pad
* Plane thermal relief
* Bottom pad
* Bottom soldermask
* Drilled hole
Soldermask. The rule mentioned earlier is also applicable to through-hole padstacks.
Pad size. The pad size is determined by two factors. First, it is at least 0.010" (0.25 mm) larger than the drilled hole size, and second, it is capable of handling the electrical current of the component lead. The larger the component lead, the larger the hole size, and the greater the potential for high current. Component manufacturers make large component lead sizes directly proportional with the amount of intended electrical current. The pad size must also be able to withstand that same current or it will become a fuse point that has the potential to heat up past the melting point temperature of the prepreg that the pad is fused to.
Anti-pad. The power plane anti-pad is the copper clearance around the drilled hole on an inner layer power or ground plane. The anti-pad size is determined by two factors. First, the PCB manufacturer requires the anti-pad size to be at least a minimum of 0.020" (0.5 mm) larger than the drilled hole and a nominal size of 0.024" (0.6 mm) larger than the drilled hole. Second, the electrical engineer does not want designers to make the anti-pad any larger than the PCB manufacturers nominal size because the anti-pad = anti-copper, or the removal of copper from the power or ground plane. It is very important in today's high-speed design layouts that every critical signal has a clean return path. If the plane anti-pads are made too large, the signal traces pass over areas void of copper and create signal integrity problems. All anti-pad sizes are in increments of .002" (0.05 mm).
Thermal relief. The power plane thermal relief has five attributes: an outside diameter, an inside diameter, a spoke width, a spoke rotation and 2 or 4 spokes. The outside diameter is typically the same size as the anti-pad. The inside diameter is typically 80% less than the outside diameter. The spoke width is typically 4X smaller than the outside diameter with 4 spokes or 3X smaller than the outside diameter with 2 spokes. The spoke rotation is normally 45[degrees] with 4 spokes. All thermal relief feature sizes are in increments of .002" (0.05 mm).
Drilled hole. The drilled hole size is typically 0.012" (0.3 mm) larger than the longest portion of the component lead size and rounded up to the nearest 0.002" (0.05 mm). All drill hole sizes are in increments of .002" (0.05 mm).
TABLE 1. Sample Naming Convention FAMILY PITCH LEAD SPAN PIN QTY ENVIRONMENT LAND PATTERN NAME SO 1.27 7.10 14 Nominal SOIC127P710-14N SOP 0.65 7.10 14 Least SOP65P710-14L SSOP 0.50 7.10 14 Most SSOP50P710-14M TSOP 0.65 7.10 14 Nominal TSOP65P710-14N TSSOP 0.50 7.10 14 Least TSSOP50P710-14L For example: SOIC: The original 0.05" pitch gullwing small outline integrated circuit. SOP: Small outline package, metric pitch device. SSOP: Shrink small outline package, when component lead pitch is less than 0.625 mm, metric pitch device. TSOP: Thin small outline package, when component height is less than 1.6 mm, metric pitch device. TSSOP: Thin shrink small outline package, metric pitch device. TABLE 2. Cylindrical end cap terminations (MELF) in mm LAND PATTERN MAXIMUM MEDIAN MINIMUM CHARACTERISTICS Level 1 Level 2 Level 3 Toe-land protrusion 1,0 0,4 0,2 Heel-land protrusion 0,2 0,1 0,0 Side-land protrusion 0,2 0,1 0,0 Courtyard excess 0,5 0,25 0,05 Round-up factor Nearest 0,5 Nearest 0,5 Nearest 0,05
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Ed.: Part II of this article will be featured in the March issue of PCD&M.
TOM HAUSNERR is CEO and director of technology for PCB Libraries Inc. He has been involved with PCB design for over 30 years. Hausherr can be reached at tom@pcblibraries.com.
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| Title Annotation: | CAD Libraries |
|---|---|
| Author: | Hausherr, Tom |
| Publication: | Printed Circuit Design & Manufacture |
| Date: | Feb 1, 2005 |
| Words: | 2270 |
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