XILINX CPLD REACHES NEW LEVELS OF LOW POWER/HIGH PERFORMANCE.
Targeted at all low power, portable systems, such as portable PCs, personal electronic companions and PDAs, and wireless devices, this unique combination of high speed and ultra low power provides designers with the best programmable logic solution available today.
New Family Features
The XPLA3 architecture, with 32 to 384 macrocells, consists of multiple logic blocks interconnected by a single level, Zero-power Interconnect Array (ZIA). Unique to each logic block is the industry's only full 36 x 48 PLA, allowing any product term to be available to any macrocell in its logic block. Product terms can also be easily expanded up to 48 per logic block without any speed penalty. The XPLA3 architecture also offers the most clocking options of any CPLD available to simplify the implementation of logic designs. In addition, the new XPLA3 family incorporates full IEEE 1149.1 JTAG functionality, 5 V tolerant I/Os, and PCI compatible I/Os.
New Markets Targeted
"To meet the demands of the battery-powered, portable market place, CPLDs will need to deliver on four key elements: power, performance, price, and size," said Evert Wolsheimer, Xilinx vice president and general manager of the CPLD division. "The XPLA3 CoolRunner products deliver on all four. Among the new uses, we envision the XPLA3 CoolRunner CPLDs to perform all typical CPLD functions: state machines, address decoding, and ASIC patches, at incredibly low power levels."
The XPLA3 family of CoolRunner devices is available in small form factor, cost-effective packages such as Quad Flat Packs (QFP) and new chip scale packages, both CP (0.5 mm pitch) and CS (0.8 mm pitch). Manufactured on a re-programmable 0.35-micron process with five layers of metal, the new family offers a very cost competitive solution. To address the need for smaller board space concerns, both chip scale packages are available in 32 and 64 macrocell devices. XPLA3 software support is available today free of charge on the Xilinx website, using the WebFITTER(SM) service, an on-line design tool, or WebPACK, a complete suite of downloadable desktop design tools. Both of these Web-powered tools offer complete synthesis, fitting, and programming file creation. Support from leading third party tool vendors, such as Aldec, Cadence/OrCAD, Exemplar, Mentor Graphics, Synopsys, Synplicity, and Viewlogic is also available.
The XCR3256XL will be the first device in the third-generation XPLA family and joins more than 130 XPLA devices ranging from 32 to 960 macrocells. Samples of the 64, 128, and 256 macrocell CPLDs are available now. High volume unit prices for the XPLA3 CoolRunner family range from $1.65 for the 32-macrocell device to $11.40 for the 256-macrocell device (100,000 units, 2H00).
Xilinx is the leading innovator of complete programmable logic solutions, including advanced integrated circuits, software design tools, predefined system functions delivered as cores, and unparalleled field engineering support. Founded in 1984 and headquartered in San Jose, Calif., Xilinx invented the field programmable gate array (FPGA) and fulfills more than half of the world demand for these devices today. Xilinx solutions enable customers to significantly reduce the time required to develop products for the computer, peripheral, telecommunications, networking, industrial control, instrumentation, high-reliability/military, and consumer markets.
For more information, call 505/798-4811.
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|Title Annotation:||CoolRunner XPLA3 complex programmable logic array|
|Article Type:||Product Announcement|
|Date:||Mar 1, 2000|
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