Printer Friendly

Voids, part 3: how to prevent voids during electroless copper deposition. (The Plating Rack).

WE HAVE ALREADY devoted two columns to voids. But there is more, much more! And until voids are eradicated from the face of the earth, or at the least, from our circuit boards, we will talk about them. This month, we look at voids as they can be directly attributed to the electroless deposition process.

Voids in the electroless copper deposit occur for a variety of reasons. Generally, the culprits are incorrect or improper maintenance of the chemical concentrations or operating parameters. Assuming that the desmear and drilling operations are within specification and not contributing to voids, however, one should next concentrate on the electroless copper process. It is important to recognize that the PTH process, as it is most commonly known, is an integrated operation. This means that the various process steps are interdependent. For example, the cleaner conditioner step influences the degree of catalyst adsorption, which in turn influences copper deposition. Thus, one can produce voids, but not necessarily because of the electroless copper solution itself. Let's explore in more detail.

The step after desmearing is to clean and condition the holes. The cleaner conditioner functions as a super wetting agent that promotes catalyst adsorption to the glass and resin. One wants to avoid incomplete conditioning of the holes, but not at the expense of overconditioning due to very long dwell times, poor rinsing and higher than normal concentrations of the conditioning chemistry. (We'll discuss the effects of overconditioning in a future column.)

The cleaner conditioner is generally a mildly alkaline solution containing wetting agents. The agents or surfactants (often formulated with cationic surfactants or polyelectrolytes) aid in the adsorption process by neutralizing the negative charges on the hole wall, particularly the glass. The supplier must formulate these conditioners so as to preferably form a monolayer of conditioner on the hole wall (as opposed to the multilayer coatings that some cationic surfactants produce). A little goes a long way. Generally, insufficient conditioning will lead to poor catalyst adsorption, particularly on the glass fibers. This conditioning will reduce the amount of catalyst adsorption and lead to poor electroless copper deposition.

The catalyst (the activator) is required in order to provide the medium that will permit the actual deposition on the copper onto the hole wall. The activator is a colloidal catalytic solution formed by the admixture of palladium chloride salts, a stannous salt in molar excess of the catalytic metal salt (palladium) all in an acidic medium. The tin is required to keep the palladium in its active state and prevent the precious metal from precipitating, rendering the activation operation useless.

Insufficient amounts of catalyst will reduce the amount of copper deposited in the hole. This will lead to either voids or reduced electroless copper plating thickness or both. Other key parameters to monitor are:

* Catalyst temperature (too low) or dwell time (insufficient); either will reduce catalyst effectiveness and cause voids.

* Palladium content on the low end of the operating window. This must be analyzed and maintained within the proper concentration window.

* Copper contamination in the catalyst (this is why operators must do everything possible to reduce copper ion drag-in from the micro-etch). Another area of concern: the pre-dip is a saltwater solution designed to provide common ion drag-in to the catalyst solution. No rinse is required. The main purpose is to reduce the chance for copper contamination in the catalyst. Generally, 500 to 700 ppm of copper in the catalyst will act as a catalytic poison, which then leads to voids.

* Oxidation of the stannous ions will subsequently lead to catalyst instability. The palladium will precipitate, thus reducing its catalytic activity. Voids will result.

* The quality of the rinse after catalyzation should not be overlooked. The rinse will remove excess catalyst and convert the stannous tin to stannic. The rinse water at this step takes on a cloudy appearance due to the conversion of the stannous tin. This actually aids in the removal of tin in the post activator step (accelerator), exposing the palladium.

* Some post activators perform their function by oxidizing the stannous tin layer that surrounds the palladium to stannic tin, creating a more catalytically active particle. Other accelerators act as a tin stripping solution, solubilizing the tin and exposing the palladium. Regardless of the mechanism or chemistry used for post activation, insufficient acceleration will reduce the copper deposition reaction. When this occurs, voids and thin deposits are the result.

FIGURE 1 shows an example of thin plating. There are several possibilities for what caused this, including insufficient conditioning of the glass fibers, insufficient catalyst adsorption in these areas or inadequate acceleration. A potential clue to the defect can be seen in the quality of the hole wall. That thin plating is showing doesn't mean that there are no voids. It may be that the section did not actually hit the voided area. Nonetheless, issues that can lead to thin plating will also cause voids. Understand how the various processes interact.

[FIGURE 1 OMITTED]

The best defense against voids and other potential defects is a good offense! Do your homework: Have a good understanding of all processes that can impact the defect.

MICHAEL CARANO is vice president of sales and marketing at Electrochemicals (Minneapolis, MN). He can be reached at mcarano@electrochemicals.com His column appears bimonthly.
COPYRIGHT 2003 UP Media Group, Inc.
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2003, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

Article Details
Printer friendly Cite/link Email Feedback
Author:Carano, Michael
Publication:Printed Circuit Design & Manufacture
Geographic Code:1USA
Date:Aug 1, 2003
Words:881
Previous Article:Conductive layer issues: why you must do more than just "view" your manufacturing data. (CAM Works).
Next Article:New angles on X-ray inspection: X-ray systems can be used in-line to identify errors prior to drilling and electrical test and trimming. (PCB Process...
Topics:


Related Articles
Drilling to the source of voids: even optimized plating can't compensate for poor hole formation or desmearing processes. (The Plating Rack).
Reducing solder voids with copper-filled microvias: a study seeks to find out the frequency, location and size of voids with and without...
New no-lead solder pastes and reflow techniques: a new study evaluated the performance of SnAgBi and SnAgCu alloys with bare copper and immersion tin...
Afraid of the dark? We'll examine the effect of severe black pad defect on solder bonds on BGAs.
Preventing hole-wall pullaway: the first steps to take to ensure good electroless copper adhesion.
Manufacturing considerations of embedded passives; designing and building PCBs with EPs means knowing the tolerances of the different material sets.
Fabrication guidelines for backdrilling: for higher designs and thick boards backdrilling--the removal of plating from the unused portion of the...
Endicott Interconnect: filling the gap: an investigation of blind and thru via fill techniques for semiconductor package and printed circuit board...
The impact of lead-free processing on interconnect reliability: lead-free assembly requires a balance between copper, base material and design to...
Metalization of high performance resin materials with a graphite-based direct plating system: graphite systems coat and then bind to resin and glass,...

Terms of use | Privacy policy | Copyright © 2021 Farlex, Inc. | Feedback | For webmasters |