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Various parametric analysis and comparison of full adder cells for DSP data path block.


DUE to increasing interest in low power ICs for portable measurement instrumentation, lap- top computers, cellular communications, etc., design choices which take into consideration low power features along with other circuit features are of the utmost importance.

Addition is the most commonly used arithmetic operation in microprocessors and DSPs, and it is often one of the speed-limiting elements [3, 4]. Hence optimization of the adder both in terms of speed and/or power consumption should be pursued. During the design of an adder we have to make two choices in regard to different design abstraction levels. One is responsible for the adder's architecture implemented with the one-bit full adder as a building block. The other defines the specific design style at transistor level to implement the one-bit full adder.

In this paper we have focused our attention on the lower design level. We have analyzed and compared the most interesting known topologies to implement a 10T full adder and 14T full adder. Moreover, considerations at architecture level deriving directly from the kind of one-bit full adder adopted are also included. The analysis and comparisons developed here have been carried out in terms of speed, power consumption and power-delay product (PDP) [4]. The investigation, which also includes the most interesting recently proposed one-bit full adders, has been based on simulation runs on a T spice process taking parasitic into account, since post layout simulations have been performed. Two design strategies have been used to size each topology. The former aims to minimize power consumption adopting minimum-size transistors, the latter achieves minimum power-delay product by suitable transistor sizing. Performance for both design strategies has been also compared for different supply voltage values.

In Section II 10T and 14T Full adder topologies are reported and briefly described. The reasons for not considering other known topologies are also looked into. In Section III, there is provided a detailed description of the simulation strategy adopted which enabled accurate and consistent results to be obtained. Then the performance of 16T, 14T and 10T Full adder topologies in terms of propagation delay [3, 14], power and PDP is analyzed and compared. More specifically, the analysis and comparison carried out in Section IV are based on transistor sizing for minimum power dissipation, while those in Section V assume a transistor sizing for minimum PDP.

Power Consumption in CMOS Circuits

The generic 1-bit conventional CMOS full adder cell is shown in Fig. 1. The 1-bit full adder cell has 28 transistors [13]. Different logic styles can be investigated from different points of view. Evidently, they tend to favour one performance aspect at the expense of others. In other words, it is different design constraints imposed by the application that each logic style has its place in the cell library development. Even a selected style appropriate for a specific function may not be suitable for another one. For example, static approach presents robustness against noise effects [12] so automatically provides a reliable operation. The issue of ease of design is not always attained easily. The CMOS design style is not area efficient for complex gates with large fan-ins. Thus, care must be taken when a static logic style is selected to realize a logic function. Pseudo NMOS technique is straightforward [11], yet it compromises noise margin and suffers from static power dissipation. Pass transistor logic style is known to be a popular method for implementing some specific circuits such as multiplexers and XOR-based circuits, like adders. On the other hand, dynamic logic facilitates the realization of fast, small and complex gates. However, this advantage is gained at the expense of parasitic effects such as load sharing, which makes the design process hazardous. Charge leakage necessitates frequent refreshing, reducing the operational frequency of the circuit. In general, none of the mentioned styles can compete with CMOS style in robustness and stability. The CMOS structure combines PMOS pull-up and NMOS pull-down networks to produce considered outputs [9]. In this style all transistors (either PMOS or NMOS) are arranged in completely separate branches, each may consist of several sub-branches. Mutually exclusiveness of pull-up and pull-down networks is of a great concern.


Full Adder Topologies Analyzed

In this paper different components have been combined to make new 16T, 14T and 10T full adder cells.


The Full adder which is the fundamental unit of the arithmetic unit. Figure 2. shows the CMOS transistor level implementation of Modified conventional CMOS full adder design using a total of 20 transistors. This type of CMOS full adder configuration has been widely used in numerous applications; it often exhibits a critical delay that actually limits the system performance. Two or more full adders are cascaded together to perform multiple bit addition. In this


System speed takes a hit, therefore to ensure better speed performance a fast full adder has been designed and it consists of 16 Transistors shown in Figure 3. The CMOS full adder based on transmission function theory they are transmission function adders (TFA). The TFA consists of 16 Transistors and dissipates less power than conventional CMOS full adders. These power savings are due to the fact that this cell has less short circuit power and that its dynamic power is lower.


The Figure 4 shows the Schematic configuration of the full adder cell consists of 14 Transistor that ensures both low power and high speed performance. It consists of 14 Transistors and occupies less area than the conventional and 16 Transistors Full adder cells. Using the power supply voltage of 3.3 V, the critical path delay of the 14 Transistor full adder cell measures at 29.56 ps while in conventional CMOS full adder it measures 31.3ps.


Another schematic configuration of the full adder cell consists of 10 Transistor that ensures both low power and high speed performance. It consists of 10 Transistors and occupies less area than the conventional, 16T and 14T Transistors Full adder cells, using the power supply voltage of 3.3V, the critical path delay of the 10 Transistor full adder measures at 24.34ps while in conventional CMOS full adder it measures 31.3ps. The power consumption also less than conventional CMOS full adder and 16T Transistors full adder. 10T has less power consumption than the other circuits. It worked successfully in low voltage power supply.

Simulation Strategies

To compare conventional, 16T, 14T and 10T full adder's performance, we have evaluated delay and power dissipation by performing simulation runs on a T Spice environment using a 0.25-[micro]m CMOS technology with same input, whose main parameters are reported in Table 1 for 5V and Table 2 for 3.3V, extracting parasitic from the layout. The simulations have been performed for different power supply voltages (3.3V, 5V), which allow us to compare the speed degradation and power reduction versus power supply of the topologies Considered. In particular, we considered four values of, equal to 3.3 V (the maximum value allowed by the technology). The last value is slightly lower than the sum of the threshold voltages of the N and P transistors.

Simulation Results

The Figure 6 and Figure 7 shows the T-spice output waveform of 20T and 16T Full Adder cell respectively.





The Figure 8 and Figure 9 shows the T-spice output waveform of 14T and 10T Full Adder cell respectively.


The full adder cells have been simulated both as a single circuit and implemented in chains, to understand the intrinsic properties and the performances in actual adder circuits. The full adder cells are simulated on T Spice at 3.3V power supply. The 10 T Transistor consume less power than other 20T,16T and 14T Full adder cells shown in Table 1 and Table 2..




Final Remarks

In this paper we have carried out a comparison among the most suitable topologies of full adder, including recently proposed ones. The information obtained is useful in the early design phases of an adder circuit, since architectural optimization.

Techniques are based on the knowledge of the full adder cell used. The full adder cells have been simulated both as a single circuit and implemented in chains, to understand the intrinsic properties and the performances in actual adder circuits. Moreover, the parasitic extracted from layout have been also considered. The paper includes the most promising recently proposed topologies, and for the well-known topologies, in some cases the results are different from those previously published in the literature (where often layout was not considered). The comparison has been carried out both assuming circuits with minimum transistors size, to minimize the power consumption, and with transistors sized to optimize the power-delay product.

The analysis has showed that the one-bit full adders without driving capability (TG and LP) are the fastest, and have power dissipation quite low; hence, they are suitable for low-power adders, even though their advantage strongly decreases reducing the power supply. In the class of 16T full adders with driving capability has very high power dissipation, greater than the CMOS, but exhibits the lowest delay. Hence, the 10 T circuit is only suitable for arithmetic circuits where no compromise on performance is allowed [Table 2]. The topology offers a more reasonable trade-off between power and delay for high performance circuits, having a delay lower than the Mirror adder, but paying a power dissipation penalty greater than the speed improvement. The 16T topology does not provide any advantage neither in terms of power nor in terms of speed, The 10 T Full adder offers only a small speed Advantage at high when transistors are minimum, thus, in general it is not a good choice. We have also shown that the advantage of the topologies without driving capability is lost in a chain of one-bit full adders increasing the number of blocks in the chain. For example consider the TG and the CMOS topologies with minimum transistors, which are the fastest and the slowest. The ratio of their propagation delays goes from about one-fifth with a 3.3 V power supply to about one-half with a 5 V power supply.

Thus at low power supply the advantage of the topology without driving capability is almost completely lost. It is worth noting that the ratio between the power consumption of topologies without driving capability with those with driving capability is maintained almost constant increasing the number of bit.


From Figure 10 and Figure 11, the 10T adder circuit has less power consumption than the other circuits. It worked successfully in low voltage power supply. In term of power consumption, conventional full adder consumes high power due to use of high power consumption XOR gate. However, that circuit consumes less power than 14T full adder. 10T use one three-transistor XNOR and one three-transistor XOR circuit. This is the reason of less power consumption in 10T circuit. Output load is one of the important parameters that affects power and performance of the circuits. 10T is the best circuit in term of power consumption for all values of output loads. The number of transistors in 9T is less than SERF and S10T but power consumption is higher than those circuits. The power of SERF changes sharply by increasing the output load value. Input frequency was changed from 50MHz to 500MHz and the effect of that was studied. 10T shows the best power consumption among all the other circuits in high frequency. 10T is suitable to use in high frequency. The 16 T full adders do not show good power consumption.


[1] A. Matsuzawa, "Low-voltage and low-power circuit Design for mixed analog/digital systems in portable equipment," IEEE J. Solid-State Circuits, vol. 29, pp. 470-486, Apr. 1994.

[2] K. Roy and S. Prasad, Low-Power CMOS VLSI Circuit Design. New York: Wiley Intersci., 2000.

[3] N. Weste and K. Eshraghian, Principles of CMOS VLSI Design (A Systems Perspective), 2nd ed. Reading, MA: Addison Wesley, 1993. ALIOTO AND PALUMBO: FULL ADDER BLOCK IN SUBMICRON TECHNOLOGY 823

[4] J. Rabaey, Digital Integrated Circuits (A Design Perspective). Englewood Cliffs, NJ: Prentice-Hall, 1996.

[5] T. Callaway and E. Swartzlander, "Low power Arithmetic components," in Low Power Design Methodologies, J. Rabaey and M. Pedram, Eds. Boston, MA: Kluwer Academic, 1996.

[6] R. Zimmermann and W. Fichtner, "Low-power logic styles: CMOS versus pass-transistor logic," IEEE J. Solid-State Circuits, vol. 32, pp. 1079-1090, July 1997.

[7] N. Zhuang and H. Wu, "A new design of the CMOS Full adder," IEEE J. SolidState Circuits, vol. 27, pp. 840-844, May 1992.

[8] H. Mahmud and M. Bayoumi, "A 10-transistor low- Power high-speed full adder cell," in Proc. ISCAS '99, Orlando, FL, June 1999, pp. 43-46.

[9] K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, and A. Shimizu, "A 3.8-ns CMOS 16_16 b multiplier using complementary pass-Transistor logic," IEEE J.

[10] Solid-State Circuits, vol. 25, pp. 388-395, Apr. 1990.

[10] H. T. Bui, Y. Wang, and Y. Jiang, "Design and Analysis of 10-Transistor Full Adders Using XOR- XNOR Gates," IEEE Trans. Circuits and Syst. II, Analog Digit. Signal Process. vol 49, no. 1, pp. 25-30, Jan. 2002.

[11] S. Veeramachaneni, M. B. Sirinivas, New Improved 1-Bit Full Adder Cells, CCECE/CGEI, Canada, 2008.

[12] A. M. shams, M. A. Bayoumi, "A Novel High Performance CMOS 1-Bit Full Adder Cell," IEEE rans. Circuits and Systems II: Analog digital Signal Process. 47 (2000), vol. 47, no. 5, May 2000.

[13] A. Kumar, M. A. Bayoumi, "Design of Robust Energy Efficient Full Adders for Deep- Sub micrometer Design Using Hybrid-CMOS Logic Style," IEEE Trans. VLSI, vol. 14, no. 12, Dec. 2006.

[14] Y. Jiang, A. Alsheridah, Y. Wang, E. shah, and J. Chung, "A Novel Multiplexer-Based Low Power Full Adder," IEEE Trans. On Circuits and Systems, vol. 51, no. 7, Jul. 2004.

[15] Ahmed M. Shams and Magdy A. Bayoumi, "A New Full Adder Cell for low power Applications", Proceedings of the IEEE Great Lakes Symposium on VLSI, 1998, pp. 45-49.

C.N. Marimuthu and P. Thangaraj

H.O.D. E.C.E., Maharaja Engg. College, Avinashi, Anna University, Tamil nadu, India Prof. & Head, C.T. Dept, Kongu Engg. College, Perundurai, Anna University, Tamil nadu, India E-mail:,
Table 1: Comparison of Power Dissipation and Delay in Various
adder cells under Vdd = 3.3 V.

Name of the CMOS Power Consumption Delay in Power Delay
Full Adder cell (e-9) (e-12) Product (e-18)

20T Model 240 31.3 7.512
16T Model 139 29.56 4.108
14T Model 130 29.56 3.842
10T Model 4.28 24.34 0.1041

Table 2: Comparison of Power Dissipation and Delay in Various
adder cells under Vdd = 5.0 V.

Name of the CMOS Power Consumption Delay (e- Power Delay
Full Adder cell (e-9) 12) Product (e-18)

20T Model 1770 40.0 70.800
16T Model 668 34.78 23.233
14T Model 500 36.73 17.927
10T Model 5.8 24.34 0.1411
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Author:Marimuthu, C.N.; Thangaraj, P.
Publication:International Journal of Computational Intelligence Research
Date:Apr 1, 2010
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