Printer Friendly

Articles from VLSI Design (January 1, 2014)

1-21 out of 21 article(s)
Title Author Type Words
A low-power scalable stream compute accelerator for general matrix multiply (GEMM). Savich, Antony; Areibi, Shawki 7038
A self-reconfigurable platform for the implementation of 2D filterbanks with real and complex-valued inputs, outputs, and filter coefficients. Llamocca, Daniel; Pattichis, Marios 8706
Design of smart power-saving architecture for network on chip. Lee, Trong-Yen; Huang, Chi-Han 4591
Design of synthesizable, retimed digital filters using FPGA based path solvers with MCM approach: comparison and CAD tool. Yagain, Deepa; Krishna, A. Vijaya 10976
Efficient hardware Trojan detection with differential cascade voltage switch logic. Danesh, Wafi; Dofe, Jaya; Yu, Qiaoyan 5728
Engineering change orders design using multiple variables linear programming for VLSI design. Fan, Yu-Cheng; Lin, Chih-Kang; Chou, Shih-Ying; Wang, Chun-Hung; Wu, Shu- Hsien; Liu, Hung-Kuan 2237
Gate-level circuit reliability analysis: a survey. Xiao, Ran; Chen, Chunhong 8938
High throughput pseudorandom number generator based on variable argument unified hyperchaos. Wang, Kaiyu; Yan, Qingxin; Yu, Shihua; Qi, Xianwei; Zhou, Yudi; Tang, Zhenan 4492
High-efficient circuits for ternary addition. Mirzaee, Reza Faghih; Navi, Keivan; Bagherzadeh, Nader 5861
Improved quantization error compensation method for fixed-width booth multipliers. Ma, Xiaolong; Xu, Jiangtao; Chen, Guican 4889
Investigation of a superscalar operand stack using FO4 and ASIC wire-delay metrics. Bailey, Christopher; Mullane, Brendan 8482
Low-area Wallace multiplier. Asif, Shahzad; Kong, Yinan 3177
Meta-algorithms for scheduling a chain of coarse-grained tasks on an array of reconfigurable FPGAs. Mehta, Dinesh P.; Shetters, Carl; Bouldin, Donald W. 10027
Novel receiver architecture for LTE-A downlink physical control format indicator channel with diversity. Abbas, S. Syed Ameer; Thiruvengadam, S.J.; Susithra, S. 5818
On the use of an algebraic signature analyzer for mixed-signal systems testing. Geurkov, Vadim; Kirischian, Lev 4963
On-chip power minimization using serialization-widening with frequent value encoding. Mohammad, Khader; Kabeer, Ahsan; Taha, Tarek 7871
Optimization of Fractional-N-PLL frequency synthesizer for power effective design. Arshad, Sahar; Ismail, Muhammad; Ahmad, Usman; Husnain, Anees ul; Ijaz, Qaiser 1709
Parallel Jacobi EVD methods on integrated circuits. Sun, Chi-Chia; Gotze, Jurgen; Jan, Gene Eu 4796
Performance analysis of modified drain gating techniques for low power and high speed arithmetic circuits. Panwar, Shikha; Piske, Mayuresh; Madgula, Aatreya Vivek 2245
Radix-[2.sup.[alpha]]/[4.sup.[beta]] building blocks for efficient VLSI's higher radices butterflies implementation. Jaber, Marwan A.; Massicotte, Daniel 5508
VLSI architectures for image interpolation: a survey. Moses, C. John; Selvathi, D.; Sophia, V.M. Anne 7615

Terms of use | Privacy policy | Copyright © 2021 Farlex, Inc. | Feedback | For webmasters |