VERPLEX SHIPS FULL-CHIP FORMAL RTL DESIGN VERIFICATION TOOL THAT CUTS LEARNING CURVE.
BlackTie was designed to be easy to use, eliminating the learning curve normally associated with formal register transfer level (RTL) design verification technology. It provides a means for exhaustive verification early in the design cycle when changes are easily fixed and less costly, and offers designers full-chip speed and capacity. In a recent customer engagement, for example, it verified more than 300,000 functional properties of a 2.7 million gate design in approximately 20 minutes using a standard Unix workstation.
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|Comment:||VERPLEX SHIPS FULL-CHIP FORMAL RTL DESIGN VERIFICATION TOOL THAT CUTS LEARNING CURVE.|
|Publication:||EDP Weekly's IT Monitor|
|Article Type:||Brief Article|
|Date:||Nov 27, 2000|
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