Ultra160/m Will Become The Preferred SCSI Implementation.
The arrival of Ultra3 SCSI and Ultral60/m SCSI builds on a long tradition of improvement in the SCSI specification and upon the lessons learned from installing over 300 million parallel SCSI products since the first SCSI specification was released. This article reviews SCSI-to-date and looks at the changes Ultra3 SCSI and Ultra160/m bring to next generation storage devices. Most importantly, this article explores what's in it for the end user.
The SCSI-3 specification has many sections. The part that codifies the SCSI Parallel Interface specification (SPI-3) is where Ultra3 SCSI is defined.. This document requires compliant product to have any one or any combination of the enhancements defined in the specification. The enhancements are double transition clocking, domain validation, cyclic redundancy checking, packetization, and quick arbitration and selection.
These features increase throughput to rates up to 160MB/sec. and improve reliability and manageability of the SCSI bus and peripherals on it, while maintaining backward compatibility. The increased bandwidth supports today's complex datatypes over the World Wide Web, the corporate Intranet, or the local area network. The improved reliability and manageability are characteristics of SCSI-based RAID arrays that are migrating up into the base technology to the benefit of all SCSI users.
If different manufacturers implement different enhancements, the opportunity for confusion and frustration with no real improvement is obvious. Seeing this, a group of leaders in the SCSI storage market, including Mylex, agreed to standardize on a specific subset of SCSI-3 features, calling them collectively Ultral6O/m, in order to minimize confusion, and bringing the benefits of the new Ultra3 features to market as quickly as possible.
The original motivation for a standards-based Small Computer Storage Interface (SCSI) was to satisfy the need for a more flexible, faster, command-controlled interface for hard disk drives and other computer peripherals. The standard provided for impressive new performance characteristics, connecting a host with as many as seven different devices, and data rates as fast as 5MB/sec. The ANSI published the first SCSI standards document in 1986. But even before that, work had already begun on the SCSI-2 standard.
Some of the new features incorporated into SCSI-2 include wide SCSI with data transfer at bus widths of 16 and 32-bits. SCSI-2 or "Fast SCSI" achieved 10MB/sec transfer rate with wider data paths of 16 and 32-bits, rising up to 20MB/sec and even 40MB/sec. It also allowed for an active terminator to improve storage subsystem integrity.
Several new commands were added and diagnostics capabilities were extended. Optional messages were added to negotiate wide transfers and to support command queuing up to 256 commands deep. Sense keys and sense codes were formalized and extended.
As Fig 1 shows, SCSI-3 is the sum of a number of separate standards. It is a family of standards, one of which is known as SPI-3 or the SCSI Parallel Interface-3. The SCSI implementations known as Ultra2 SCSI and Ultra3 SCSI fall into this area.
Ultra160/m: A Rational Subset
There are strong parallels between the evolution of the early SCSI standard in 198586 and today's efforts to group some of the features from Ultra3 SCSI into a subset called Ultral6O/m. The early specification was modified by industry leaders to increase the mandatory requirements for compliance with the standard. The Common Command Set evolved out of this effort by a consortium of manufacturers who were motivated to improve interoperability and user satisfaction.
The SPI-3, of which Ultra3 SCSI is a part, states that, for a product to be SCSI3 compliant, it needs to include only one of the new features defined in the specification, similar to the ambiguity around the early command set in the SCSI-i specification. Ultra3 SCSI products can include .any of the following features: double transition clocking or CRC (Cyclic Redundancy Check) or domain validation or packetization, or QAS (Quick Arbitration and Select).
Once again, a group of industry leaders have agreed to tighten the requirements for early implementations of the Ultra3 portion of the SPI-3 specification. Mylex, Fujitsu, Hewlett-Packard, IBM, LSI Logic, Quantum, and others have announced support for a subset of the Ultra3 specification called Ultra160,m SCSI. Given its critical mass of support, this subset is likely to initially become the industry's preferred implementation. The earliest implementations of Ultra160/m SCSI are coming onto the market now. General industry availability is expected late in 1999. Ulta160/m includes the first three features, double transition clocking, domain validation, and cyclical redundancy checking (Fig 2).
Double Transition Clocking
Ultra160/m SCSI doubles transfer rates to 160MB/sec by using both edges of the request/acknowledge signal to clock data. Double transition clocking enables speeds of up to 160MB/sec without increasing the interface clock rate and while using existing Ultra2 SCSI cable plants.
Double transition clocking changes the digital protocol to use both edges of the SCSI request/acknowledge signal to clock data. Simply increasing the speed of the data lines can double data transfer rates. Fig 3 illustrates that the request/acknowledge signal on UItra2 SCSI runs at 40MHz, while data runs at only 20MHz or 80MB/sec on a 16-bit wide bus. By using both edges of the same 40MHz request/acknowledge signal, the data rate can be increased to 40MHz or 160MB/sec on a 16-bit wide bus, as Fig 4 shows. The increased interface bandwidth is an essential ingredient for Windows NT and Unix workstations, video and Web servers, and Storage Area Networks (SANs).
Cyclical Redundancy Checks (CRC)
Ultra160/m reliability enhancements include the addition of a Cyclical Redundancy Check (CRC) on, data. CRC provides protection against marginal cable plants, poorly connected external devices, and is one of the best ways to assure data protection during hot plugging. CRC calculates a 32-bit polynomial; sector-level checksum, to verify the integrity of transferred data, the same proven process that is utilized by FDDI, Ethernet, and Fibre Channel interfaces. CRC detects all single bit errors, all double bit errors, all odd number of errors, all burst errors up to 32bits long, and has a -2-32 rate of undetected random error patterns.
Domain Validation detects the configuration of the SCSI bus, automatically testing and adjusting the SCSI bus transfer rate to optimize interoperability. Once two devices on the bus have negotiated a speed, the initiator sends out a Write Buffer command to the device to test transfers at the negotiated speed. The initiator will then read back and compare the data and check for parity and CRC errors. If the test fails, the initiator will repeat the test at the next lower speed, until a compatible speed is detected. User data will not be transferred until an optimum speed is proven. If reliability is at risk, the transfer proceeds without a hitch at a lower speed--much the way today's modem and fax transmissions connect despite variations in equipment.
Domain Validation should increase end-user satisfaction and decrease total cost of ownership by reducing service calls for under-performing systems. If the SCSI bus or Storage Area Network appear unreliable, an Ultral60/m SCSI device can reduce transmission speed to ensure accurate data throughput, potentially saving on technical support resources and alleviating end-user frustration.
The Ultra160/m interface is backward compatible, so you'll be able to run current SCSI devices with future products such as Ultra160/m RAID controller boards. Domain Validation helps assure that Ultra160/m devices operate smoothly in legacy systems. Testing is done automatically without changing controller settings, setting BIOS parameters, or fumbling with manuals.
Other Ultra3 SCSI improvements beyond the near term definition of Ultral60/m include packetization, and Quick Arbitration and Selection.
Packetization reorganizes and compresses the current SCSI command and data transfer process from seven down to three phases, eliminating the overhead associated with the higher number of phase changes. Bus overhead is reduced once by combining command and message phases prior to a data transfer into a single packet. Bus overhead is reduced again by combining the status and message phases that follow a data transfer. The reduction in overhead is most noticeable during smaller data transfers, such as transaction processing.
Packetization also changes the timing on command, message, and status phases from asynchronous to synchronous. (In previous versions of SCSI, command transfers were asynchronous, which is slower than data transfers.) Both of these changes are aimed at improving available bandwidth, critical in video, graphical, and scientific applications.
Quick Arbitration And Selection
Quick Arbitration and Selection or QAS is another protocol specified in SCSI-3. It eliminates idle time or overhead on the SCSI bus. QAS allows devices to skip the bus free phase in the current SCSI protocol. As a device with QAS-enabled monitors buses traffic, it will arbitrate for the bus right after the last device on the bus has sent a disconnect, instead of waiting for the disconnect and the bus free phase. QAS provides faster arbitration to reduce connect/disconnect time on SCSI bus and contributes to higher performance levels in random I/O environments such as database, account inquiry, and transaction processing. QAS is enabled by negotiation and is compatible with legacy devices.
A significant implementation challenge in QAS is in the development of a fairness algorithm to prevent devices with higher priority on the SCSI bus from starving other devices with lower priority. QAS has the potential to keep more spindles busier, which means better I/O performance in small file environments like database, OLAP, and OLTP systems.
What Does It All Mean?
Ultra 160/m and full Ultra3 beyond that offer a stable, broadly supported implementation of SCSI-3 that promises measurable benefits to end users in the forms of increased bandwidth, better bus reliability, and better performance in I/O intensive applications. All without requiring a new cable plant or expensive transceivers.
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|Title Annotation:||Technology Information|
|Publication:||Computer Technology Review|
|Date:||Jul 1, 1999|
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