ULTRA-LOW VOLTAGE VDBA DESIGN BY USING PMOS DTMOS TRANSISTORS.
Keywords: VDBA, DTMOS, Low Voltage, Filter.
The growing demand for ultra-low voltage (ULV), ultra-low power (ULP) and high performance electronic devices and VLSI circuits are attracting significant interest for the scientists and special markets and they have grown rapidly. Power consumption is an important criterion for the continued development of the microelectronic technology . The power consumption has been concerned as a critical parameter particularly for portable electronic devices, medical electronics implant devices and battery powered devices. Dropping the power dissipation of the circuit is necessary to keep battery life much longer than usual. Reducing the power dissipation is easily and effectively possible by lowering the power supply voltage, however, dropping the supply voltage is causing some problems due to the CMOS evolution. One of them is the signal headroom becomes too small to design circuits with sufficient signal integrity and the other problem is the gate leakage . These problems are hindering the designing ULV and ULP electronic devices. These problems can be fixed by using the DTMOS transistors.
Several analog signal processing and signal generation circuits have been designed by the current-mode techniques. Various number of active elements, detailed reviews are given in , have been proposed based on different applications. These active elements were designed with either changing the input or output terminal, or changing the control parameter as external current or voltage. These active elements were designed by modifying, reshaping or manipulating the basic elements such as voltage feedback amplifiers, current feedback amplifiers, transconductance amplifiers and current conveyors. The literature surveys show that considerable amount of current mode filters using different type of active blocks have been proposed by several authors. These reported realizations including different active building blocks such as Current Differencing Buffered Amplifiers (CDBAs) [3-6], first generation Current Conveyors (CCI), second generation Current Conveyors (CCIIs) [7-12], Operational Transconductance Amplifiers (OTAs) [13-15], Differential Voltage Current Conveyors (DVCCs) [16-18] and Current Differencing Transconductance Amplifiers (CDTAs) [3,19-24]. The Current Differencing Buffered Amplifier (CDBA) was firstly proposed by Acar and Ozoguz in 1999 . The Voltage Differencing Buffered Amplifier, namely VDBA, which has low output impedance and high input impadence, is proposed in  as an alternative to the CDBA. The only differences between the CDBA and VDBA are the signal types of inputs. While input terminals of the VDBA are voltage, the input terminals of the CDBA are current. Fully Balanced Voltage Differencing Buffered Amplifier (FB-VDBA) was firstly published by Biolek and others in . In , the new CMOS realization of VDBA and its filter applications was proposed. In this circuit, it needs 3V supply voltage and its power consumption is 0.97 mW.
In this study, the dynamic threshold voltage metal oxides semiconductor (DTMOS) transistors based VDBA circuit and its new filter application is proposed. The circuit can be performed by an ultra-low supply voltage 0.4 V and it is total power consumption is only 6.22 nW. The transistors have been used in weak inversion for the purpose of the lower power consumption. Because of their well subthreshold slope characteristic, the DTMOS transistors are very desirable for working under the ultra-low voltages. It is seen from the simulation results both proposed VDBA and the filters have performed very well. The proposed DTMOS-based VDBA circuit is appropriate for ULV and ULP biomedical and analog signal processing applications.
2. DTMOS Based VDBA Design
Assaderaghi and others proposed the Dynamic Threshold voltage MOSFET (DTMOS) for silicon on insulator (SOI) process technology [27-29] in 1994. As shown in Figure 1 , the body terminal of the transistor is tied to gate terminal to generate the DTMOS whose threshold voltage utilizing the relation in Eq. 1;
[mathematical expression not reproducible] (1)
where where [empty set]_0 is the total surface band bending, [gamma] is body effect coefficient, VTO is the zero bias threshold voltage. The proposed DTMOS has a high threshold voltage at zero bias and low threshold voltage at Vgs = Vdd.
The threshold voltage equation is written for a long channel NMOS transistor where drain-induced barrier lowering (DIBL) effect is neglected. The DTMOS configuration does not require any additional processing steps fabrication and the gate and body of the transistor can be connected with metal contact as described in Silicon-On-Insulator (SOI) model . DTMOS was proposed for obtaining excellent subthreshold characteristics at ultra-low Vdd [27-29]. Although PMOS transistors can be connected easily as DTMOS transistor, NMOS transistors require triple-well process which is very expensive processes to produce DTMOS transistor with their own wells. Only PMOS transistors have been used as a DTMOS in this study. Voltage headroom has been consumed over the NMOS transistors so overall performance of the proposed active device is limited. MOS transistor's drain current is given by below Eq. (2).
[mathematical expression not reproducible] (2)
According to the equation high frequency applications and strong inversion operations are not possible using this circuit because the transistor will saturate in weak inversion when VDS [greater than or equal to] 3kT/q . Under some limitations, bulk-DTMOS technique can be applied to cheap standard CMOS fabrication process without additional processing steps. The transconductance gm is described by
[g.sub.m] =q [[I.sub.D]/nkT] (3)
The Block diagrammatic representation of proposed VDBA circuit symbol is shown in Figure 2. According to the figure p and n terminals are input, z and w terminals are output. The voltage difference is realizing with the differential-input OTA. Differential input voltage is transferred to the current at the terminal z by transconductance gain and the voltage drop at the terminal z is mirrored the terminal w which is the low impedance voltage output region. OTA, voltage controlled current source, has a high differential input stages and output stage. Electrical impedance transformation from one circuit to other is provided by buffered amplifier which is connected to the OTA's current output.
The relation between terminal currents and voltages of the VDBA can be characterized by the following matrix:
[mathematical expression not reproducible] (4)
Vp and Vn are the high-impedance voltage inputs, Iz is the high-impedance current output and Vw is the low-impedance voltage output can be noted by above matrix. The internal construction of DTMOS based ULV and ULP proposed VDBA circuit is shown in Figure 3. This active device consists of an Operational Transconductance Amplifier (OTA) and a voltage buffer. The input stage of VDBA is composed of the differential-input OTA and the voltage buffer is connected to its current output. The transistors from M1 to M9 work as the OTA and the transistors from M10 to M16 work as the buffer amplifier. The transistors from M1 to M5 and M11 to M13 are the PMOS DTMOS. DTMOS transistors, which have available voltage headroom, can be used efficiently under the ultra-low supply voltage of 0.4V [27-29].
The circuits have been simulated by using LTSpice program with TSMC CMOS 0.18 [micro]m process parameters. Table 1 shows the aspect ratios of the transistors for the proposed VDBA circuit. Supply Voltages are Vdd = -Vss = 0.2 V and all the biasing voltages are grounded in this application (Vb1 = Vb2 = Vb3 = 0 V).
The DC transfer characteristics of proposed VDBA input and output stages are shown in Figure 4 and Figure 5, respectively. The DC transfer characteristic of Iz against Vp for VDBA is shown in Figure 4 that is obtained when the terminal n which is the one of the input terminal is grounded. The DC transfer characteristics of Vz-Vw for the VDBA is shown in Figure 5. While the lower boundary of the voltage Vw for VDBA is determined as VWmin = 145 mV, the upper boundary of voltage Vw for VDBA is the positive supply voltage of the VDBA. It can be summarized that input voltage swing is between -145 mV to 200 mV under [+ or -]200 mV supply voltages. The AC transfer characteristics of input and output stages of proposed VDBA are shown in Figure 6 and Figure 7, respectively. The transconductance of proposed active circuit's gm is depicted in Figure 7 where it is found approximately 64 nA/V with a 3dB bandwidth of 3.66 kHz. The circuit performance of the proposed VDBA is summarized in Table 2.
3. The Filter Application of Proposed VDBA
The performance of the proposed active element was analyzed with a biquad filter application. The voltage-mode filter is illustrated in Figure 8. The filter consists of two VDBA devices and two capacitors. The capacitance values of C1 and C2 are 100 pF. The transfer function can be expressed depending on the voltage status of V1 and V2. The filter is obtained different types of filter depending on voltage status of V1 and V2. The four filter functions are summarized in Table 3.
Figure 9 shows that responses of proposed VDBA based filters such as Low-Pass Filter (LPF), High-Pass Filter (HPF), Band-Pass Filter (BPF), and Band-Reject Filter (BRF).
The pole frequency ([omega]_0) and the quality factor (Q) are given by Eq. (5) and Eq. (6), respectively, for all the responses;
[mathematical expression not reproducible] (5)
[mathematical expression not reproducible] (6)
The passive sensitivities of the pole frequency ([omega]_0) and the quality factor (Q) for the proposed configuration with respect to active and passive elements yield;
[mathematical expression not reproducible] (7)
[mathematical expression not reproducible] (8)
It is clearly observed from Eq. (7) and Eq. (8) that passive and active sensitivities of pole frequency ([omega]_0) and quality factor (Q) for the proposed configuration do not exceed unity in magnitude. Temperature is an important factor for very low frequency filters with large time constants. The temperature has been changed from 0 [degrees]C to 75 [degrees]C and results are shown in Figure 10. Output total harmonic distortion (THD) values of the proposed filter at the 100 Hz frequency with respect to the input voltage are depicted in Figure 11. The total harmonic distortion of the filter obtained is less than 2% for inputs not exceeding 50 mV peak to peak voltages as shown in Figure 11. The obtained results show that the THD remains within acceptable limits.
In this study, DTMOS-based VDBA circuit was proposed. The proposed active circuit is able to work with 0.4 V voltage and only consuming 6.22 nW, which are suitable value for ultra-low voltage and ultra-low power operations. The proposed VDBA was tested with an application example of the filter. The LTSpice simulation results were depicted and according to simulations, both VDBA and filter have performed very well. Sensitivity analyses and percent of the total harmonic distortion has been found. The proposed active block has been worked in weak inversion area, so the working frequency is not very high. It works in low frequencies. It is believed that the proposed DTMOS based VDBA circuit and filter will be useful in the design of ULV and ULP analog signal processing applications and biomedical applications.
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Muhammed Emin BASAK (1), Firat KACAR (2)
(1) Faculty of Naval Architecture and Maritime, Yildiz Technical University, 34349, Istanbul, Turkey
(2) Istanbul University, Department of Electrical & Electronics Engineering, 34850, Istanbul, Turkey firstname.lastname@example.org, email@example.com
Received on: 15.06.2017
Accepted on: 10.07.2017
M. Emin Basak He received his B.Sc, M.Sc., and Ph. D. degrees from Istanbul University in all in Electrical and Electronics Engineering 2005, 2008, 2014, respectively. Basak has performed research from 2007 to 2008 in I'ESIGELEC, IRSEEM Institutes, Rouen, France. He is currently an Assistant Professor at Faculty of Naval Architecture and Maritime at the Yildiz Technical University. His general research interests modelling, simulation of electronic devices and electronic circuits.
Firat Kacar He received his B.Sc, M.Sc. and Ph.D. degrees from Istanbul University in all in Electrical and Electronics Engineering 1998, 2001 and 2005. He is currently Professor at the Electrical and Electronics Engineering Department of Istanbul University. His current research interests include analog circuits, active filters, synthetic inductors; CMOS based circuits' electronic device modeling and hot-carrier effect of MOS transistors. He is the author or coauthor of about 70 papers published in scientific journals or conference proceedings.
Table 1. MOSFET dimensions used in VDBA simulations. Transistor Width Length [M.sub.1], [M.sub.2], [M.sub.3], [M.sub.10], [M.sub.11] 5 [micro]m 2 [micro]m [M.sub.4], [M.sub.5], [M.sub.12], [M.sub.13] 300 [micro]m 2 [micro]m [M.sub.7], [M.sub.8], [M.sub.14], [M.sub.15] 50 [micro]m 5 [micro]m [M.sub.6], [M.sub.9], [M.sub.10], [M.sub.16] 100 [micro]m 5 [micro]m Table 2. Performance summary of the proposed VDBA Technology 0.18[micro]m TSMC Supply Voltage [+ or -]200 mV Input Voltage Range -145 mV - +200 mV Power Consumption 6.22 nW Transconductance 64 nA/V Input Impedance (n terminal) 500 G[OMEGA] Input Impedance (p terminal) 877 G[OMEGA] Output Impedance (z terminal) 5.26 M[OMEGA] Output Impedance (w terminal) 205 Table 3. The filter functions depending on the input and output status. Input Voltage Status Output Function [V.sub.1]=[V.sub.in], [V.sub.2]=0 [mathematical expression not reproducible] (LPF) [V.sub.1]=0, [V.sub.2]=[V.sub.in] [mathematical expression not reproducible] (BPF) [V.sub.1]=0, [V.sub.2]=[V.sub.in] [mathematical expression not reproducible] (HPF) [V.sub.1]=[V.sub.in], [V.sub.2]=[V.sub.in] [mathematical expression not reproducible] (BRF)
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|Title Annotation:||voltage differencing buffered amplifier; dynamic threshold voltage MOS transistors|
|Author:||Basak, Muhammed Emin; Kacar, Firat|
|Publication:||Istanbul University - Journal of Electrical & Electronics Engineering|
|Date:||Jul 1, 2017|
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