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Total Ionizing Dose Effects of Si Vertical Diffused MOSFET with Si[O.sub.2] and [Si.sub.3][N.sub.4]/Si[O.sub.2] Gate Dielectrics.

1. Introduction

Silicon power MOSFET, especially vertical diffused MOSFET (VDMOS), is widely used for high power application due to its mature technology and cost efficiency. Nowadays, VDMOS is often used under harsh environment such as space, where it suffers from cosmic radiation [1-4]. To operate normally in space environment, Si VDMOSs must be able to withstand ionizing radiation such as total ionizing dose (TID). In this paper, we investigate TID effects in Si VDMOS with different gate dielectrics including single Si[O.sub.2] layer and double [Si.sub.3][N.sub.4]/Si[O.sub.2] layer, different oxidation temperatures of Si[O.sub.2], and different gate bias during irradiation.

2. Experiment Set-Up

The Si VDMOSs considered here are devices with well-known standard fabrication process except the gate dielectric deposition condition. Different silicon dioxide deposition conditions are carried out including different oxidation temperature from 800[degrees]C to 1000[degrees]C and with and without postoxidation annealing. In particular, double gate dielectric layer [Si.sub.3][N.sub.4]/Si[O.sub.2], having the same total thickness 50 nm (20 nm/30 nm) as that of single Si[O.sub.2] layer, is fabricated to evaluate its hardness towards TID.

The irradiation test is performed with unpackaged devices wire-bonded on the test board under [Co.sup.60] gamma source at a dose rate of 50 rad (Si)/s at room temperature, and the devices are remeasured after a total dose of 100 Krad is reached after 33 minutes. Irradiation was performed with different gate voltages ([V.sub.G]) of 10 V, 0 V, and -5 V, with source terminal grounded and drain terminal of small voltage to guarantee a small current of about 100 mA for [V.sub.G] = 10 V and drain terminal of 200 V (rated breakdown voltage). The bias-stress-only test is also performed without irradiation to account for the electrical stress influence, such as [V.sub.TH], [g.sub.m]. The bias-stress test is carried out by using the same biases ([V.sub.G] of 10 V, 0 V, and -5 V) and time (33 minutes) comparable to those used in the irradiation experiments. Current-voltage characteristics are measured using Agilent 2902A parameter analyzer, and the measurements are carried out before and right after the irradiation/bias-stress.

3. Results and Discussion

Figure 1 shows [I.sub.D] versus [V.sub.G] characteristics of Si VDMOS with different gate dielectrics and different oxidation conditions before and after TID irradiation with [V.sub.G] = 10 V during irradiation. Two types of gate dielectrics with the same total thickness of 50 nm are investigated including normal Si[O.sub.2] layer (Figure 1(a)) and double [Si.sub.3][N.sub.4]/Si[O.sub.2] layer (Figure 1(b)), which is claimed to be more TID tolerant [5-9]. It can be observed that the threshold voltage [V.sub.TH] shifts negatively for single Si[O.sub.2] layer indicating a net holes' trapping during positive-bias irradiation, and [DELTA][V.sub.TH] increases from 0.2 V to 0.71 with rising oxidation temperature from 800[degrees]C to 1000[degrees]C. The high temperature annealing (HTA) step after oxidation adds to the negative shift, suggesting a higher hole trapping ability. However, for double [Si.sub.3][N.sub.4]/Si[O.sub.2] layer, [V.sub.TH] shifts positively at [V.sub.G] = 10 V with a smaller [DELTA][V.sub.TH] = 0.14 V than that of Si[O.sub.2]. It can be explained that, at positive-bias irradiation with [V.sub.G] = 10 V, as shown in Figure 5(a), the irradiation created electrons in the Si[O.sub.2] layer are swept to the [Si.sub.3][N.sub.4] and trapped there, forming net electrons trapping by compensating with the irradiation created holes in [Si.sub.3][N.sub.4] [10-12]. The number of electrons trapped in the [Si.sub.3][N.sub.4] is higher than the holes trapped in the Si[O.sub.2], resulting in a net positive [V.sub.TH] shift.

Figure 2 shows [g.sub.m] versus [V.sub.G] characteristics of Si VDMOS with different gate dielectrics and different oxidation conditions before and after TID irradiation with [V.sub.G] = 10 V during irradiation. It can be observed that the devices with both single Si[O.sub.2] dielectrics and double [Si.sub.3][N.sub.4]/Si[O.sub.2] dielectric (Figures 2(a) and 2(b)) have about the same [g.sub.m] value both before and after a total dose of 100 Krad (Si), indicating excellent gate control. The device with double [Si.sub.3][N.sub.4]/Si[O.sub.2] dielectric (Figure 2(b)) shows higher [g.sub.m] of 1.6 S compared to that of single Si[O.sub.2] layer (1.3~1.4 S) at [V.sub.D] = 1 V, which is due to a higher effective gate capacitance. The capacitance of [Si.sub.3][N.sub.4]/Si[O.sub.2] gate dielectric is measured to have a gate capacitance of 1.6 x [10.sup.-9] F, while Si[O.sub.2] gate dielectric has a gate capacitance of 1.1 x [10.sup.-9] F due to a higher dielectric constant of [Si.sub.3][N.sub.4] with the same total thickness.

To exclude the electrical stress response from the bias irradiation test, the bias-induced degradation was separately measured at biases and times compared to those used during irradiation. The results show that the electrical stress has trivial influence (<5%) on [V.sub.TH] compared with the TID bias irradiation effects.

Figure 3(a) shows [DELTA][V.sub.TH] of different gate dielectrics at different gate biases during irradiation including [V.sub.G] = -5 V, [V.sub.G] = 0 V, and [V.sub.G] = 10 V. It can be observed that, for single gate dielectric Si[O.sub.2] with different oxidation conditions, [V.sub.TH] shifts all negatively, and the Si[O.sub.2] layer fabricated at lower temperature presents a smaller [V.sub.TH] shift at all gate biases during irradiation. It can also be observed that the threshold voltage [V.sub.TH] shifts the most at irradiation bias of [V.sub.G] = 0 V for single Si[O.sub.2] gate dielectric. It can be explained that, at [V.sub.G] = 0 V, the irradiation created holes are freely dangling around in Si[O.sub.2], which are more easily trapped in the Si[O.sub.2], forming positive trapped charges, leading to negative [V.sub.TH] shift. For irradiation bias of [V.sub.G] = -5 V, there are similar chances that irradiation created holes can be trapped in the Si[O.sub.2], while, simultaneously, irradiation created electrons are swept to the Si[O.sub.2]/semiconductor interface, forming more interface defects than in the case of irradiation bias of [V.sub.G] = 0 V, which can be confirmed by calculating, respectively, the [V.sub.ot] and [] values by subthreshold midgap technique (SMGT) [12, 13], as is shown in Figure 3(b).

In an ideal device, the drain current and gate voltage are related by [I.sub.D] ~ exp([V.sub.G]) in subthreshold regime. When plotted as log([I.sub.D]) versus [V.sub.G], the straight I-V characteristic can be extrapolated to a calculated midgap current. Comparing the preirradiation and postirradiation characteristics, the midgap voltage shift, [DELTA][], as well as the change in subthreshold swing (inverse slope), [DELTA]S, can be determined. The value of [DELTA][] is equivalent to [DELTA][V.sub.ot] and [DELTA]S is proportional to [DELTA][]. The subthreshold charge separation technique has proven to be the easiest to perform and is the most widely used. The value of [DELTA][V.sub.ot] is obtained from [DELTA][] assuming the following relation:

[mathematical expression not reproducible] (1)


[mathematical expression not reproducible] (2)

The difference between the pre- and postirradiation subthreshold swings, AS, is calculated by the following relations:

[mathematical expression not reproducible] (3)

where [] stands for the interface trap induced capacitance, k is the Boltzmann constant, T is the temperature, and the Fermi potential [0.sub.B] can be calculated as follows:

Figure 3(b) shows [DELTA][V.sub.ot] and [DELTA][] calculated by SMGT method using (1) to (4) of both single gate dielectric Si[O.sub.2] and double gate dielectric [Si.sub.3][N.sub.4]/Si[O.sub.2] at different gate bias including [V.sub.G] = -5 V, [V.sub.G] = 0 V, and [V.sub.G] = 10 V. It can be observed that, for single Si[O.sub.2] dielectric, [V.sub.ot] are similar in both [V.sub.G] = -5 V and [V.sub.G] = 0 V, while [] is larger in [V.sub.G] = -5 V than in [V.sub.G] = 0 V, resulting in a compensation of [V.sub.TH] effects.

The [V.sub.TH] shifts negatively at all bias irradiation cases for single Si[O.sub.2] gate dielectric layer; for double gate dielectric [Si.sub.3][N.sub.4]/Si[O.sub.2], however, [V.sub.TH] shifts negatively in [V.sub.G] = -5 V, and [V.sub.TH] shifts positively in [V.sub.G] = 10 V and barely shifts in [V.sub.G] = 0 V. By calculating [V.sub.ot] and [], respectively, it can be observed that, at [V.sub.G] = -5 V, more holes are swept to wards/to the [Si.sub.3][N.sub.4] layer, where they can be more easily trapped compared to Si[O.sub.2] [5]. For [V.sub.G] = 10 V, irradiation created electrons are trapped in [Si.sub.3][N.sub.4], forming negative trapped charges, leading to positive [V.sub.TH] shift.

Under bias irradiation, electron/hole pairs are being generated in a MOSFET. At [V.sub.G] = 0 V, electrons/holes get more chances to recombine at first, forming less trapped holes and interface defects. At [V.sub.G] = -5V or [V.sub.G] = 10 V, less electrons/holes recombine at higher electric field, leading to more trapped holes and interface defects, as illustrated in Figure 4.

Figures 4(a) and 4(b) show the calculated [DELTA][N.sub.ot] and [DELTA][] values of both single gate dielectric Si[O.sub.2] and double gate dielectric [Si.sub.3][N.sub.4]/Si[O.sub.2] at different gate bias including [V.sub.G] = -5 V, [V.sub.G] = 0 V, and [V.sub.G] = 10 V. It can be observed that, at [V.sub.G] = 0 V, single gate dielectric Si[O.sub.2] and double gate dielectric [Si.sub.3][N.sub.4]/Si[O.sub.2] show similar value of [], indicating similar Si[O.sub.2]/semiconductor interface, which is logical due to the same oxidation condition. With increasing absolute gate bias |[V.sub.G]|, more interface defects are created for both dielectrics.

For single gate dielectric Si[O.sub.2], the oxide trapped charges [N.sub.ot] increase with the absolute electric field |E|, with the least oxide trapped charges at [V.sub.G] = 0 V due to recombination of more holes/electrons at the beginning. For double gate dielectric [Si.sub.3][N.sub.4]/Si[O.sub.2], there are more net oxide trapped charges at [V.sub.G] = -5V than at [V.sub.G] = 10 V, which can be explained as follows.

Under positive-bias irradiation, the charges in the Si[O.sub.2] are mostly due to holes trapping at the oxide/silicon interface. In contrast to this, the negative charges due to the electrons from the oxide layer and the positive charges due to the holes from the nitride compete to determine both the magnitude and the sign of the charges in the [Si.sub.3][N.sub.4], as illustrated in Figure 5(a). The electrons generated in the oxide layer are swept to the nitride layer easily because no electron barrier exists at the [Si.sub.3][N.sub.4]/Si[O.sub.2] interface. The total number of holes generated in the oxide and escaping initial recombination is assumed to be approximately proportional to the oxide thickness, which is consistent with what is observed in Figure 4(a) with more [N.sub.ot] in single Si[O.sub.2] layer than in double [Si.sub.3][N.sub.4]/Si[O.sub.2] layer at [V.sub.G] = 10 V.

For negative bias irradiation, [Si.sub.3][N.sub.4]/Si[O.sub.2] shows negative [V.sub.TH] shift, larger in magnitude than that for positive-bias irradiation. This occurs because the nitride/oxide interface has more trapped holes than trapped electrons due to the holes moving from the Si[O.sub.2] without hole barrier at the interface, as illustrated in Figure 5(b). Also, some of the holes generated in the oxide are trapped in the oxide. Due to the net trapping of holes in both the oxide and nitride, there is addition of charges for the negative bias case [10-13].

4. Conclusions

The gate dielectric effects and gate bias dependence of TID effects on Si VDMOS have been evaluated. Single gate dielectric Si[O.sub.2] presents negative [V.sub.TH] shift at either positive or negative gate bias, which improves with lower oxidation temperature. Double gate dielectric [Si.sub.3][N.sub.4]/Si[O.sub.2] shows negative [V.sub.TH] shift at negative gate bias due to net holes trapping in [Si.sub.3][N.sub.4]/Si[O.sub.2] and positive [V.sub.TH] shift at positive gate bias due to net electron trapping.

These results provide insight into the mechanisms and magnitude of the TID responses of Si VDMOS with Si[O.sub.2] and [Si.sub.3][N.sub.4]/Si[O.sub.2] gate insulators, and [Si.sub.3][N.sub.4]/Si[O.sub.2] is proved to be more TID tolerant.

Conflicts of Interest

The authors declare that there are no conflicts of interest regarding the publication of this paper.

Authors' Contributions

Author Min Zhou has been added as coauthor and corresponding author with all authors' agreement. Dr. Min Zhou helps with the paper revision including paper writing and deep analysis about the microstructure of the defects responsible for trapping.


The research is supported by the National Natural Science Foundation of China (Grant 61604128), the Scientific Research Fund of Zhejiang Provincial Education Department (Grant Y201533913), and the Fundamental Research Funds for the Central Universities (Grant 2016QNA4025).


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Jiongjiong Mo, (1) Xuran Zhao, (2) and Min Zhou (1)

(1) School of Aeronautics and Astronautics, Zhejiang University, Hangzhou, China

(2) School of Computer and Information Engineering, Zhejiang Gongshang University, Hangzhou, China

Correspondence should be addressed to Min Zhou;

Received 19 June 2017; Accepted 6 September 2017; Published 15 October 2017

Academic Editor: Gerard Ghibaudo

Copyright [c] 2017 Jiongjiong Mo et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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Title Annotation:Research Article
Author:Mo, Jiongjiong; Zhao, Xuran; Zhou, Min
Publication:Active and Passive Electronic Components
Article Type:Report
Date:Jan 1, 2017
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