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Toshiba leads in 65-nanometer CMOS process technology with lowest power consumption transistor for mobile products.

Toshiba Corporation recently announced a major advance in 65-nanometer (nm) CMOS process technology that will bring high levels of performance and low power consumption to next generation LSIs for mobile products. Using a new gate dielectric material, Toshiba has developed a CMOS transistor that reduces gate leakage current to a level only 1/1000 that of CMOS transistors with conventional gate dielectrics. The company replaced the usual silicon dioxide in the transistor gate dielectric with nitrided hafnium silicate (HfSiON), a high dielectric constant (high-k) material, and confirmed its performance. Toshiba now plans to apply the new process to the mass production of system LSIs for mobile products in 2005.

Toshiba leads the semiconductor industry in the development of advanced process technology, including 90nm CMOS process technology for mass production of systems LSIs. Last December, Toshiba, with Sony Corporation, announced the development of the world's first 65-nanometer (nm) CMOS process technology for embedded DRAM system LSIs for high performance products. Today's announcement of a 65nm process technology suited to next generation mobile products, which must combine high-speed performance with low power consumption, confirms Toshiba's continuing lead in essential technologies for advanced generations of system LSIs.

The thickness of the gate dielectric in LSI grows progressively thinner with each new generation of CMOS process technology. However, that thinness can cause larger gate leakage current. This is emerging as a critical issue, especially in low power products, such as mobile terminals, and it has spurred a search for thicker gate dielectric materials offering the same performance as SiO2. HfSiON, nitrided hafnium silicate, is recognized as a promising material, but there are few reports of any practical fabrication process that can be applied to mass production. Toshiba has developed a fabrication process for HfSiON gate dielectric film for 65nm low power CMOS applications and confirmed its characteristic with an experimentally fabricated LSI with 50nm gate-length CMOS transistors.
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Publication:EDP Weekly's IT Monitor
Geographic Code:9JAPA
Date:Jun 16, 2003
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