Tool cognition: when the CAD tool "understands" how other product design tools function, a better system is the result.
Increased complexity of SoCs and the growth in multi-die packaging have spurred attention to cross-domain collaboration among the IC, package substrate and PCB design groups. High-pin-count devices, coupled with cost sensitivity, have forced engineers to reconsider how they plan and optimize I/O placement on their chips, while making tradeoffs involving complex IC packaging variables--potentially, all while targeting multiple, different board-level platforms.
Cognitive design. To be most useful, EDA tools should be cognitively aware of the tools used in other processes. In the package and PCB design world, there has been little awareness of each other. True, FPGA pinouts can be defined to a limit by the customer, but "standard" parts have generally not offered this option.
[FIGURE 1 OMITTED]
By making tools aware of the design and processes used in other segments of product design, those tools are able to work together to produce a better system design in a much shorter time frame. Further, standard IC dies can be packaged in different ways, depending on the form factor of the end product to realize more optimal solutions for each.
A perfect example of how tools will soon be more cognizant of each other and work together to produce more optimal designs is the design of a smartphone and a tablet using the same CPU die. Obviously, many mobile device companies are doing precisely that. However, the available real estate on a tablet PCB will likely be significantly greater and have fewer constraints than a smartphone. So, a package for the CPU on a tablet may be larger, have different pinouts, or may be able to dissipate more power than the same CPU in a smart phone. Thus, a single "standard" package may not be the optimum package for either application (FIGURE 1).
Using new tools, designers now can take the die configuration and "look" at the design from either the perspective of the package and transfer to the PCB (the traditional method), or look at the requirements of the PCB design and work backward to the package design. And, they have the capability to take each product using that CPU and work backward from the PCB to the optimal package specifically for that design optimization.
From the packaging viewpoint, the physical design rules are written by the PCB design requirements. Then, the tool interactively works with the rules and the package designer to implement a package that is optimum for that particular application of the chip. This relatively quick method to design the package also allows exploration of different ideas to quickly find the optimum.
FIGURE 2 shows a hypothetical product design. In this case, the form factor of the final product is known, and preliminary placement of the components has been made. Note in the top illustration that placement of the CPU has been reserved. With this input, the tools can begin path finding, that is trying multiple package configurations based on the rules that both the PCB designer and the package designers have written.
With each design, a conditional routing can be made on the PCB to determine the best package and pin-out. Rules allow designers to define such parameters as leaving corner pins unused, keeping differential pairs together, how to distribute power and ground, how to handle data and address busses, etc.
Once the rules have been written, it is not quite "push the button and sit back," but it is straightforward and considerably quicker and more accurate than using spreadsheets and pin lists, which is the current status quo.
The advantages of tool-cognitive designs and being able to optimize a design in any of the design domains are significant. First, it becomes much easier to tailor multiple package designs to allow the optimum use of a given component in the required form factor. Designs can be looked at from multiple "what if" scenarios, such as smaller footprint, least cost, simplest breakout and exit, etc. Second, the sheer number of pins has simply overloaded the capability of constructing package designs using spreadsheets and pin lists. The chance of error is near 100% when humans are entering data for hundreds of pins. And, of course, the benefits of increased quality, optimum package for the form factor, and reduction of errors are multiplied by the time saved in the overall system design.
[FIGURE 2 OMITTED]
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|Title Annotation:||DESIGNER'S NOTEBOOK|
|Publication:||Printed Circuit Design & Fab|
|Date:||Nov 1, 2013|
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