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Testing ICs without breaking the (power) budget.

Saying that advanced ICs are complex is an understatement. The seemingly endless progression to smaller geometries, the ever-increasing integration between analog and digital blocks, and the diminishing voltage supply are just some of the factors contributing to the complexity of today's chips. Add to this the need for energy efficiency in portable and wireless IC designs, and the level of concern over power use and control during production test that is on the rise.

Two major metrics dictating test costs are test-vector volume and execution time. As a result, the goal for automatic test pattern generation (ATPG) is to achieve the maximum coverage with the minimum number of test patterns. This conflicts with the goals of managing power because, to get the highest quality test results, the IC usually is operated beyond its normal functional modes during test.

When running production tests, switching activity can exceed the limits of the chip's power structures and package. This, in turn, can produce false failures and, in some cases, cause permanent damage. As a result, switching activity is one of the constraints that must be considered during the ATPG process. But this consideration has to be balanced with the goal of creating efficient, high-quality production test patterns.

Common fail modes that can occur when switching activity exceeds a device's power capability during test include the following:

* Collapse of the power supply

* Switching noise

* Excessive current that leads to joule heating and connection failure

The first two effects commonly lead to false failures. The third can result in permanent damage when wires and via connections experience electromigration that causes a shortening of a device's lifetime and, in extreme cases, immediate failure.

Power management must be tackled during both design and the testing process. Modular partitioning, power-domain gating, and clock gating are all techniques used to manage dynamic and static power dissipation at the system level.

Control Switching Activity Using Modular Test

A modular test approach leverages the existing hierarchical/modular structure inherent in most SOC designs to manage the switching activity during production test by sequencing test activity and controlling power on a block-by-block basis. While not an explicit ATPG technique, this method requires configuring pattern generation so that active blocks are only considered during the ATPG process and the remaining blocks are held in a steady state.

Figure 1 shows an example of a design partitioned into several modules with each module's scan chains accessible at the top level. Multiplexers are used to select modules that are being targeted at a given phase of the test.


The number of phases is determined by the switching activity limit and the coverage required. The number of phases may exceed the number of modules because of additional configurations needed to achieve coverage of the top-level interface logic. The blocks not being tested can be held in a steady state using clock gating, reset assertion, or steady-state scan.

A modular test approach can be further enhanced with block-based test-compression insertion, which also can improve top-level routing. Testability of an individual block can be improved with test-point insertion and logic BIST, potentially reducing the switching activity needed to reach the power goals as well as the target fault coverage.

Take Control of Power Domains During Test

Power-domain gating controls power by switching off the supply to inactive portions of a design to save both dynamic and static power dissipation. In this mode of operation, ATPG needs to take into account the power-control structures and generate patterns that operate within the confines of the selectable power configurations.

The structure and operation of the various power structures are described in standards such as Unified Power Format (UPF), which currently is going through the process of IEEE standardization as P1801. UPF/P1801 can be used as a constraint method in the implementation phases of a design as well as a description of design intent that can be used for rule checking.

UPF/P1801 describes power domains and how they map to the logic structure and hierarchy and lists control methods and modes. It defines logic connections between power domains and whether they can be isolated and whether they need level shifting or logic level retention if the driver power supply is removed. Some of the more common power structures used in production test include power switching logic, retention cells, isolation cells, and level shifters.

Because power-domain switching and the additional cells and structures used in its implementation can adversely affect scan operation and ATPG, new rules must be developed to ensure that scan testing is effective. Typical rules that need to be checked include the following:

* Correct definition of power modes

* Correct control of power modes

* Correct connection of scan path and control logic through multiple power domains

* Correct operation of the scan path through switchable power domains

* Correct control of power domains through scan load, capture, and unload cycles

Testing power-domain switching logic can be performed by implication or direct observation. When testing by implication, the incorrect operation of a circuit within a switched domain has to be detected by cycling the power control logic while exercising the circuit within the switched domain so an incorrect state on a retention cell within the domain can be observed. This method relies on retention cells being present and usually requires a complex ATPG test sequence.

The second and preferred method is to insert an observe point at the output of the power control logic to explicitly detect a failure. Retention and isolation cells between domains can be tested by toggling power domains and checking that the appropriate values are observable at the block boundaries. As with testing of the power-switching logic, this method requires both control of the switching logic and control and observability of the retention and isolation cells through scan elements.

Level shifters can be tested with standard stuck-at and transition tests because they are effectively buffers with different input and output thresholds.

How to Control Switching Activity During Scan Test

Complementing these techniques is the capability to modify the way ATPG patterns are created so that the level of switching activity is considered as a constraint. Various ATPG strategies can be used to control switching during the load, capture, and unload phases of scan test. For example:

* Fault and pattern selection criteria based on switch threshold

* Fill strategies for don't-care bits

* Clock gating control

Fault and Pattern Selection Criteria Based on Switch Threshold

In standard ATPG, pattern generation targets the maximum number of faults in the minimum number of patterns. This approach leads to high levels of switching activity, usually in the early part of the test set. Switching activity then tails off toward the end of the test set as more targeted heuristics are used to capture the faults that are demanding in terms of control and observation.

By relaxing the rate of fault detection and setting a switching threshold as part of the initial constraints for ATPG, the coverage attainment rate is spread out more evenly through the entire test set.

Fill Strategies for Don 't-Care Bits

A nonintrusive method of controlling load-switching activity is to use a constant fill for don't-care bits that normally would be in a random state. This minimizes transitions during scan shift for load/unload.

Figure 2 shows how a fill strategy would be used with test-pattern compression. The constant fill is accomplished with a combination of masking and additional encoding bits in the decompressor.


A more intrusive method of controlling switching during shift is to suppress the scan flop data output; that is, to hold the Q output constant during scan shift and prevent switching in the logic paths connected to it. This approach requires creating a separate scan shift path and adding a gate delay to control the Q output in the design's functional path. The use of constant fill also indirectly affects capture power because it typically creates less switching capture activity than patterns with a random fill for don't-care bits.

While this approach guarantees reduced switching activity, it has an adverse effect on the design's functional path delay, which may be unacceptable. However, the approach need not be used on all scan elements to achieve significant reductions in power.

Clock-Gating Control

A more direct method of controlling capture power is to use clock-gating control to hold elements in a constant state that are not being used to control or observe targeted faults. ATPG must be able to control the clock-gating logic using either scan elements or primary pins to control clock-switching activity. Hierarchical clock controls can provide a finer level of control granularity while using fewer control bits.

Combining Strategies

Depending on the power needs and areas of concern, these techniques also can be used in combination. However, some methods are mutually exclusive. For example, you must choose between fill for either capture or scan shift because their implementations conflict. The production test designer must decide which techniques to use while considering the trade-off of benefits based on design constraints and priorities.

A pragmatic approach is to see if coverage and pattern size goals can be met within the power threshold of the design by using the nonintrusive techniques that leverage the existing structure. If this is not possible, then more intrusive techniques, such as scan flop output freezing, can be selectively used to bring the production test power under budget.


Traditionally, production test is planned relatively late in the design cycle. However, to control switching activity during test without compromising test quality, production test requires earlier consideration to maximize its effectiveness. As with most design constraints, controlling power during production test has an associated cost and must be balanced with the rest of the design goals.

By leveraging features already in place at the system level to control power dissipation during normal device operation, power used during production test also can be effectively managed. When design-level approaches to power control are combined with ATPG techniques, you can achieve high-quality test results while satisfying power integrity needs.

About the Author

Giri Podichetty is a technical marketing engineer in the Design-for-Test Division at Mentor Graphics. He has more than 18 years of ASIC design experience in most aspects of design implementation from inception to final tape-out. Mr. Podichetty received a bachelor's degree in engineering from Tesside University, United Kingdom. Mentor Graphics, 8005 S. W. Boeckman Rd., Wilsonville, OR 97070, 503-685-7033, e-mail:

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by Giri Podichetty, Mentor Graphics
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Title Annotation:IC TEST; integrated circuits
Author:Podichetty, Giri
Publication:EE-Evaluation Engineering
Geographic Code:1USA
Date:May 1, 2009
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