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Test & measurement software: boundary-scan tools extend beyond basic PCB testing.

Although introduced 16 years ago, the IEEE 1149 standard continues to help engineers who must test electronic products. The 1149 standard has the formal name, "IEEE Standard Test Access Port and Boundary Scan Architecture." Engineers often refer to it as simply "boundary scan" or "JTAG"; the latter stands for Joint Test Action Group, the group that launched the standardization effort.

Companies that produce boundary-scan testing tools continue to extend the underlying technology beyond basic tests for opens and shorts on a printed circuit board (PCB). The standard and new developments now encompass device programming, built-in self test (BIST) structures, remote testing and other capabilities. To understand the state of techniques and products, we talked with several vendors of boundary-scan tools.

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ASSET Intertech

To extend boundary scan, the IEEE recently formed the P1687 working group to develop a standard that lets engineers access test and debug structures within complex ICs. But, the internal JTAG (IJTAG) structures will still communicate with an external tester through a standard 1149.1 four-wire interface.

Glenn Woppman, President and CEO of ASSET Intertech, explained the original 1149.1 standard does not easily handle the control of internal operations or internal debug operations. "Say my ASIC contains a malfunctioning adder," said Woppman. "Implementing an internal test structure would let me try bit combinations to see what happens. I might find only certain combinations cause addition errors." The P1687 group addresses giving boundary-scan software access to that type of internal ASIC debug structure. Today, the group has an architecture up for discussion.

On the tool front, ASSET Intertech has devoted time and energy to making its ScanWorks software easier to use by providing a new GUI and by automating some tasks. "We have put models on the Web so customers can download them. Our tools read the models' information and automate as many steps as possible," said Woppman. "And ScanWorks will automatically check for updates." In addition, ASSET Intertech offers short video instructions and demonstrations that let engineers quickly start to use the ScanWorks tools. "If you forget something such as how to program a Flash memory or a CPLD, a five-minute video gets you started," said Woppman.

Corelis

Because many engineers want a test system that does not require a variety of add-on pods and modules and because so many computers now come with PCI Express slots, Corelis has introduced the market's first boundary-scan controller card that plugs into a PCI Express slot. Menachem Blasberg, President of Corelis, noted companies often must ship test systems to regional facilities and to contract manufacturers. Thus, the simpler the test system, and the fewer the components, the easier it becomes to set up and use. The card directly handles the test vectors produced by Corelis' Scan ExpressTPG Test Pattern Generator software, and it supports parallel testing and programming of multiple boards and devices.

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Due to the popularity of devices with [I.sup.2]C and SPI ports, Corelis has added direct [I.sup.2]C and SPI-based memory programming capabilities to its ScanExpress boundary-scan software and hardware. The [I.sup.2]C and SPI interfaces operate independent of the JTAG test port, so one boundary-scan controller can simultaneously test a PCB and program onboard devices.

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Unlike boundary-scan programming, which relies on long bit streams to transfer data and address information, access through an [I.sup.2]C or an SPI port lets device programming proceed at close to the maximum speed a device supports. Additionally, access through an [I.sup.2]C or SPI port with the Corelis interface gives engineers access to internal chip operations they may not have access to through a boundary-scan port.

Goepel

The latest release (Ver. 4.3) of the CAS-CON software tools from Goepel supports the IEEE 1149.6 standard (also known as AC JTAG), which targets testing digital circuits that incorporate high-speed AC-coupled and differential connections. This standard extends test capabilities so boundary-scan techniques can test circuit components such as high-speed serialization/deserialization (SERDES) ICs and differential transmitters and receivers.

Goepel also has extended its proprietary boundary-scan programming language, CASLAN, which underlies the company's software tools. Although use of CASLAN is optional, many engineers use it to write their own test sequences or applications and still capitalize on standard boundary-scan techniques. A CASLAN program can produce tests that automatic test-pattern generator (ATPG) tools might not create. And because Goepel has its own language, it can expand it to adapt to new mixed-signal or nonstandard boundary-scan tests. Those tests can apply Scanflex I/O modules that extend testing beyond boundary-scan capabilities.

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"To test a DAC, for example, boundary-scan devices give you access to the digital inputs, but they cannot test the analog output," said Heiko Ehrenberg, Manager for U.S. Operations for Goepel. "So, engineers can use a Scanflex I/O module to measure the voltage output. Statements in the CASLAN-based software can gather the voltage data and determine whether the DAC operated properly. The tests all take place within the boundary-scan framework." Although other vendors offer similar "off-board" modules for digital tests, Ehrenberg believes so far only Goepel provides for this type of analog testing. The company's VarioCore-IP technology lets engineers develop new Scanflex-module functions through software, or engineers can use Goepel's standard functions.

Intellitech

C. J. Clark, President and CEO of Intellitech sees two areas of interest in the boundary-scan world--concurrent test and embedded test. "Because boundary-scan operations can take a long time, engineers want to run tests and program devices on many boards simultaneously," said Clark. Concurrent JTAG, or CJTAG, which Intellitech implements in its PT100 parallel tester, provides many boundary-scan ports that run simultaneous test and programming operations. By balancing the time needed to load and unload PCBs against the time needed to run tests, engineers can achieve production throughput based solely on handling time and not test time, which results in what Clark calls "zero test time."

Intellitech also offers its SystemBIST chip that lets designers put stand-alone built-in self-test (BIST) capabilities on a PCB. The chip serves as an FPGA configuration device that can execute boundary-scan tests and store the results. People can later retrieve test results for pin-level diagnostics, which avoids the need to re-run tests at the factory. The chip saves costs because it simplifies field updates of FPGAs and eliminates the no-fault-found results and false alarms associated with a software-only test approach. Because SystemBIST chips do not require training or automatic-test equipment to run tests, they provide an economic way to deploy boundary-scan test capabilities at contract manufacturers. And, tests can run during environmental stress screening, burn-in testing and under field conditions.

The SystemBIST chip costs less than $15, and engineers can buy an evaluation kit to try the hardware and software. "You can import tests from other boundary-scan tools and FPGA configuration data; then you control how the chip will apply tests and configuration data at power-up," Clark noted.

JTAG Technologies

TapCommunicator technology from JTAG Technologies lets engineers test and program a system over an existing communication channel, no matter its length. It comprises an uplink module, located near a boundary-scan controller and a downlink module embedded in the system under test. The signal integrity is as robust as that of the network, and communications can include fault detection and retransmission capabilities.

"TapCommunicator spans just about any distance between a boundary-scan tester and a device under test," said Ray Dellecker, U.S. Marketing Manager of JTAG Technologies. "And the product will work with every 1149.1-based test system on the market." A number of companies are investigating TapCommunicator for use in their products.

JTAG Technologies also has released ProVision, a new boundary-scan development tool that enhances usability. The new software automates more tasks and lets engineers see as much, or as little, of the detail as they choose. ProVision also takes care of non-boundary-scan devices automatically by using models that describe device attributes. "When you combine device models and boundary-scan description [BSDL] files, the tools know how to set up tests on a PCB," explained Dellecker. "Previously, engineers would have to manually set up non-boundary-scan devices so they would not interfere with the tests." No library can cover every device, so ProVision comes with a model editor that lets engineers create models by entering device information in forms or templates.

ProVision integrates testing and flash and CPLD programming tasks and operates with all existing JTAG Technologies production systems. Thus, customers can preserve their hardware investments and can continue to use legacy test files.

The online version of this article includes the sidebar: "Test Tool Excels at Debug Time." Visit www.ecnmag.com and click on "Current Issue."

For Further Reading

* Bleeker, Harry, Peter van den Eijnden and Frans de Jong, Boundary-Scan Test: A Practical Approach, Kluwer Academic Publishers, Boston. 1993.

* Eklow, Bill and Ben Bennetts, New Techniques for Accessing Embedded Instrumentation: IEEE P1687 (IJTAG)," Eleventh IEEE European Test Symposium, 2006. pp. 253-254. http://doi.ieeecomputersociety.org/10.1109/ETS.2006.33.

* Boundary Scan Tutorial," Corelis. www.corelis.com/products/Boundary-Scan_Tutorial.htm.

* IEEE 1149.6, "Boundary Scan Testing of Advanced Digital Networks," http://grouper.ieee.org/groups/1149/6/.

* ScanWorks with IEEE 1149.6 High-Speed Interface Testing," ASSET Intertech. www.assetintertech.com/products/jtag_ieee11496_1.htm.

by Jon Titus, Senior Technical Editor

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Author:Titus, Jon
Publication:ECN-Electronic Component News
Article Type:Cover story
Date:Nov 1, 2006
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