Tensilica Introduces TurboXim Fast Functional Simulator 40-80x Faster than ISS, Automatic SystemC Model Generation.
SANTA CLARA, Calif. -- Tensilica[R], Inc. today announced the new TurboXim[TM] fast functional simulator, which is 40 to 80 times faster than Tensilica's proven cycle-accurate ISS (Instruction Set Simulator). Tensilica also introduced its ability to automatically generate SystemC models to match all possible configurations of its Xtensa[R] configurable processors and Diamond Standard series processors. These introductions significantly speed ESL (embedded system level) design and architectural exploration for SOC (system-on-chip) design using one or more Xtensa configurable processors or Diamond Standard processors.
"As SOC designs continue to grow to tens of millions of gates, we need to continue giving designers powerful tools at higher levels of abstraction," stated Steve Roddy, Tensilica's vice president of marketing. "Our fast TurboXim simulator will help designers move up to system-level design, providing for much better SOC planning from the start of the design process. And designers will have the flexibility to use automatically-generated C-level models using either standard C/C++ or SystemC."
TurboXim for Fast Functional Simulations
The new TurboXim fast-functional simulator simulates the instruction set of Xtensa or Diamond Standard processors. By using native-compiled code techniques, Tensilica was able to achieve speeds 40 to 80-times faster than its standard ISS. The TurboXim simulator delivers a peak performance of over 180 million cycles per second on highly iterative code (such as a matrix multiplication DSP kernel), a sustained 50 million simulation cycles per second on complex code running on a typical Xtensa or Diamond Standard processor, and even delivers a sustained 25 million cycles per second on more complex simulations, such as simulating an AAC (Advanced Audio Coding) audio decoder on a VLIW (Very Large Instruction Word) audio DSP processor configuration. (Note: Simulator speeds cited are for single-core simulations running on a Linux workstation with a 3 GHz Opteron 256 processor.) This enables SOC designers and software developers to simulate Xtensa and Diamond processor software at speeds similar to running in an FPGA prototype or emulation environment and a meaningful fraction of the speed that the processor will run in the actual target SOC.
TurboXim is extremely useful for software development and functional verification. When coupled with XTSC or XTMP models (see below) of Xtensa or Diamond Standard processors, a SOC designer can create a system model of their entire chip and perform fast functional verification, as well as provide a very efficient software development environment.
Tensilica anticipates most customers will also perform hybrid simulations using TurboXim and its ISS. In a hybrid simulation, an application developer can choose to simulate different parts of the same application using either simulator and dynamically switch between them. This allows the designers to collect statistical profiling information of the entire application or detailed profiling information for only the most important parts of the application.
XTSC: Automated SystemC Model Generation
Tensilica's XTSC (XTensa SystemC) SystemC 2.1 models support both the Diamond Standard series of processors and designer-defined Xtensa processor configurations, including all designer-defined customizations. Tensilica's Xtensa Processor Generator automatically generates XTSC models for each unique configuration of the Xtensa 7 and Xtensa LX2 processors. This automation adds to the freedom that Tensilica offers designers to create unique Xtensa processor configurations that are optimized to different tasks.
Tensilica's SystemC models can be used with both Tensilica's standard cycle-accurate instruction set simulator (ISS) or the new TurboXim fast functional simulator. Because SystemC is an emerging industry standard, Tensilica's customers can leverage a large and growing third party eco-system of SystemC consultants and EDA vendors to create models of their SOC designs early in the design process.
Tensilica continues to offer its proprietary XTMP (XTensa Modeling Protocol) system-level modeling environment for designers who want a flexible, powerful yet simpler C-based modeling environment for high-level system design. XTMP provides a true multi-processor environment, including memory modeling of both local and system memories. XTMP provides a wide variety of options for implementing, controlling, and displaying results of system simulations deploying multiple cores, memories, and user-defined devices. (Note: SystemC is a C++ based modeling environment. XTMP provides the user a conventional ANSI C interface API.)
Multiple Processor Design Enhancements
Tensilica made other enhancements aimed at further improving a software developer's productivity when coding for multiple processor SOC designs. An improved multiple processor debug capability has been integrated into Tensilica's Xtensa Xplorer[TM] integrated design environment that enables SOC designers to debug XTMP and XTSC simulations of multi-processor designs, as well as the target SOC hardware itself, all from the same debug environment. This debugger works with simulations based on both the cycle-accurate ISS and the fast functional TurboXim simulator. Furthermore, the enhanced multiple processor debugging tools seamlessly enable synchronous debugging of multiple-processor system hardware. This means that a developer can choose either to break (or stop) the execution in each processor individually or to simultaneously halt execution in all processors.
Pricing and Availability
The TurboXim fast functional simulator is priced at $2000 per seat and is available now. The system simulation option, which delivers both Tensilica's XTSC and XTMP models, is priced at $2000 per seat and is available now. Tensilica's software developer's toolkit, which includes the high performance Xtensa C/C++ compiler, the cycle-accurate Xtensa instruction set simulator, the Xtensa Xplorer integrated design environment, and a complete set of utilities and libraries, and is priced starting at $2000 per seat for floating node licenses.
Tensilica offers the broadest line of controller, CPU and specialty DSP processors on the market today, in both an off-the-shelf format via the Diamond Standard Series cores and with full designer configurability with the Xtensa processor family. Tensilica's low-power, benchmark proven processors have been designed into high-volume products at industry leaders in the digital consumer, networking and telecommunications markets. All Tensilica processor cores are complete with a matching software development tool environment, portfolio of system simulation models, and hardware implementation tool support. For more information on Tensilica's patented approach to the creation of application-specific building blocks for SOC design, visit www.tensilica.com.
* Tensilica and Xtensa are registered trademarks belonging to Tensilica, Inc. Xplorer is a trademark of Tensilica, Inc. All other company and product names are trademarks and/or registered trademarks of their respective owners.
* Tensilica's announced licensees include Afa Technologies, ALPS, AMCC (JNI Corporation), Aquantia, Astute Networks, Atheros, ATI, Avago Technologies, Avision, Bay Microsystems, Berkeley Wireless Research Center, Broadcom, Cisco Systems, Conexant Systems, Cypress, Crimson Microsystems, ETRI, EE Solutions, FUJIFILM Microdevices, Fujitsu Ltd., Hudson Soft, Hughes Network Systems, iBiquity Digital, Ikanos Communications, LG Electronics, Lucid Information Technology, Marvell, MediaWorks, NEC Laboratories America, NEC Corporation, NetEffect, Neterion, Nethra Imaging, Nippon Telephone and Telegraph (NTT), NuFront, NVIDIA, Olympus Optical Co. Ltd., PnpNetwork Technologies, sci-worx, Seiko Epson, Solid State Systems, Sony, STMicroelectronics, Stretch, TranSwitch Corporation, u-Nav Microelectronics, Validity Sensors, Victor Company of Japan (JVC), WiQuest Communications and XM Radio.
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|Date:||Jan 22, 2007|
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