TSMC delivers 20nm and CoWoSTM design reference flows.
Taipei, Oct. 12, 2012 (CENS) -- Taiwan Semiconductor Manufacturing Co. (TSMC) recently delivered two foundry-first design reference flows supporting 20nm and Chip on Wafer on Substrate (CoWoSTM) process technologies, demonstrating its readiness of the design flow references within its Open Innovation Platform (OIP).
According to the world's No.1 pure foundry, its 20nm Reference Flow enables 20nm design with DPT aware capabilities to reduce design complexity and deliver required accuracy. DPT enablement includes pre-coloring capability, new RC extraction methodology, DPT sign-off, physical verification and DFM. In addition, TSMC and its ecosystem partners design 20nm IP for DPT compliance to accelerate 20nm process adoption.
The CoWoSTM Reference Flow enables 3D IC multi-die integration and allows a smooth transition to 3D IC with minimal changes in existing methodologies. The flow includes the management of placement and routing of bumps, pads, interconnections, and C4 bumps; innovative combo-bump structure; accurate extraction and signal integrity analysis of high-speed interconnects between dies; thermal analysis from chip to package to system; and an integrated 3D testing methodology for die-level and stacking-level tests.
TSMC vice president of R&D, Dr. Cliff Hou, pointed out that these reference flows give designers access to TSMC's advanced 20nm and CoWoS technologies. Delivering advanced silicon and manufacturing technologies as early and completely as possible to the company's customers is a chief goal for TSMC and its OIP design ecosystem partners, he stressed.
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|Title Annotation:||Chip on Wafer on Substrate|
|Publication:||The Taiwan Economic News|
|Article Type:||Brief article|
|Date:||Oct 12, 2012|
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