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TSMC Validates Cadence Parasitic Extractor on Processes Down to 0.18 Micron; Cadence Assura HyperExtract Tool Key to Leading-Edge Timing-Driven-Design Flow.

SAN JOSE, Calif.--(BUSINESS WIRE)--July 5, 1999--

Cadence Design Systems, Inc. (NYSE: CDN) today announced that Taiwan Semiconductor Manufacturing Company (NYSE: TSM), the world's leading pure-play foundry, has validated the Cadence(R) Assura(TM) HyperExtract parasitic extraction tool on processes down to 0.18-micron.

The tool is a key component of the system-level-constraint-based, timing-driven-design (SLC-TDD) flow that Cadence is offering to the foundry's customers ("Cadence and TSMC Develop Foundry-Specific, Timing-Driven Toolkit for SOC Designs," July 5, 1999).

To validate Assura HyperExtract, TSMC performed calibration with the foundry's field solver on hundreds of test structures created with the Cadence tool, as well on real-life designs, with submicron geometries of 0.25 and 0.18 micron. In all cases, Assura HyperExtract produced results within 10 percent of the foundry's prescribed standards. The consistency and predictability of these results led TSMC to validate the Cadence tool.

"To model deep-submicron effects, our customers need tools that provide the highest level of accuracy, and the Cadence extractor offers this benefit," said Andley Chang, Marketing Manager, Design Services, TSMC. "In addition, it is key to the SLC-TDD flow that we have worked with Cadence to create, making it an even better supported solution throughout our foundry for customers who select the entire flow."

Several benchmarks performed by Cadence customers show Assura HyperExtract leading competitors in performance -- in some cases, by orders of magnitude -- while providing comparable accuracy. Assura HyperExtract is also integrated with the Cadence Envisia(TM) Silicon Ensemble(TM) place-and-route tools, so customers who plan to implement the latter will not have to set up the extractor separately. This will provide customers who choose the Cadence parasitic extractor with even greater assurance of first-pass design success.

"TSMC's validation is an important milestone for Assura HyperExtract," said Jim Hogan, vice president of IC Implementation marketing at Cadence.

"We have worked hard to ensure that this tool provides all the functionality and accuracy that designers need. Through its exhaustive benchmarking process, TSMC has verified our success in this endeavor, and our customers now have access to an extraction solution that provides best-in-class accuracy and performance. We look forward to future successes in our ongoing relationship with TSMC."

Pricing and Availability

To enhance customer access to Assura HyperExtract, TSMC offers downloadable rule files for the tool from its website (http://www.tsmc.com.tw). Supported interfaces include LEF/DEF and GDSII. Assura HyperExtract is U.S. list-priced at $125,000 (single-user, node-locked).

About Cadence

Cadence Design Systems, Inc. is the largest supplier of software products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With more than 4,000 employees and 1998 annual sales of $1.2 billion, Cadence is headquartered in San Jose, Calif. and has sales offices, design centers, and research facilities located around the world. More information about the company, its products and services may be obtained from the World Wide Web at http://www.cadence.com.

About TSMC

TSMC (ADS traded NYSE: TSM, also traded on TSE) is the world's largest dedicated integrated circuit (IC) foundry and offers a comprehensive set of IC fabrication processes, including processes to manufacture CMOS logic, mixed-mode, volatile and non-volatile memory and BiCMOS chips. Currently, TSMC operates two six-inch wafer fabs (Fab 1 and 2) and three eight-inch wafer fabs (Fab 3, 4, and 5), all located in Hsin-Chu, Taiwan. TSMC also delivers wafers from its first U.S foundry, WaferTech, a joint venture with Altera, analog Devices and Integrated Silicon Solution, Inc. TSMC has broken ground in the new Tainan Park, which will house Fabs 6 and 7 and recently announced its participation in a $1.2 billion joint venture fab with Philips Semiconductor which is scheduled to open in Singapore in 2000.TSMC's corporate headquarters are in Taiwan. More information about TSMC is available through the World Wide Web at http://www.TSMC.com.

Cadence and the Cadence logo are registered trademarks and Assura, Envisia and Silicon Ensemble are trademarks of Cadence Design Systems, Inc. All others are properties of their holders.
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Date:Jul 5, 1999
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