TRANSWITCH UNVEILS MULTI-CHANNEL PROTOCOL CONTROLLER.
The MCHDLC VLSI device joins TranSwitch's growing family of programmable VLSI products giving users unprecedented levels of system integration and device flexibility. The MCHDLC is developed to address a growing market demand for lower power, higher port density, greater flexibility commonly required in packet access applications today, and cost effectiveness. The MCHDLC device can be complemented with TranSwitch's broad portfolio of feature rich octal framer devices, T1Fx8 and E1Fx8, to deliver one of industry's most comprehensive and highest density access chipset solutions.
The MCHDLC is a full duplex, 256-channel HDLC controller that provides interfaces for as many as eight independent serial data streams. Each serial interface can support a variety of line rates, configurable in one of four formats: T1 channelized (framed) or unchannelized, E1 channelized (framed) or unchannelized. Optionally, the device can support up to two serial interfaces with line rates of up to 8 Mbits/s in an unchannelized format. The MCHDLC VLSI device performs Layer-2 HDLC formatting/de-formatting at data rates from 8 Kbits/s up to 2.048 Mbits/s. This allows the MCHDLC to support hyper-channels (Nx64 Kbits/s) or any number of bits in a DS0 for sub-channeling applications (Nx8 Kbits/s). Processed data is transferred to the host memory across a 32-bit Peripheral Component Interconnect (PCI, Rev 2.1 compliant) bus with a bandwidth of 33 MHz in both master and slave modes. The PCI configuration information is entered via a serial EEPROM interface.
The MCHDLC allows transmit or receive rate adaptation using external SRAM buffer space. A standard on-chip TranSwitch ACE RISC Processor manages the control of data transfers between off-chip rate adaptation memory and PCI bus system memory using TranSwitch-supplied firmware. With one of the industry's highest off-chip rate adaptation memory support, and additional intelligence implemented in firmware, the tolerance of PCI bus latencies is significantly enhanced. This benefits users by allowing better statistical multiplexing advantage on the PCI bus; more MCHDLCs can be interconnected, with lower system cost. This translates to increased efficiency for the user in deploying bandwith.
"The MCHDLC is ideally suited for ISDN D-Channel processing, Internet Service Provider (ISP) access server, Remote Access Concentrator (RAC), WAN and ADSL server, T1/E1 LAN router, Frame Relay Access Switching Systems and T1/E1 packetized links from Wireless Base Stations applications - all of which are high growth market segments," stated Steve Lam Product Manager at TranSwitch Corporation.
The design support package for the MCHDLC includes a PCI add-in card, device firmware, reference device driver software, PC evaluation software, user manual, data sheet, BSDL files, a reference schematic and full applications support from TranSwitch - all the essentials needed to accelerate customers' time-to-market.
MCHDLC is packaged in a 304-pin BGA package, requires a single 3.3V power supply, and supports 5V tolerant signal I/Os. IEEE 1149.1 boundary scan is also supported. MCHDLC engineering samples are available immediately, and production quantities will be available in late 2Q99.
TranSwitch Corporation, headquartered in Shelton, Connecticut, is a leading developer and global supplier of innovative high-speed VLSI semiconductor solutions - Connectivity Engines(TM) - to original equipment manufacturers who serve three fast-growing end-markets: the Worldwide Public Network Infrastructure, the Internet Infrastructure and corporate Wide Area Networks (WANs). Combining its in-depth understanding of applicable global communication standards and its world-class expertise in semiconductor design, TranSwitch Corporation implements communications standards in VLSI solutions which deliver high levels of performance. Committed to providing high quality products and service, TranSwitch is ISO 9001 registered.
For more information, call 203/929-8810.
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|Date:||Jun 1, 1999|
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