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Study of complex gate structures in quantum cellular automata technology.

Introduction

Quantum dots are nanostructures created from standard semi conductive materials. These structures are modeled as quantum wells. They exhibit energy effects even at distances several hundred times larger than the material system lattice constant. A dot can be visualized as well. Once electrons are trapped inside the dot, it requires higher energy for electron to escape. Quantum dot cellular automata is an Novel technology that attempts to create general computational functionality at the nanoscale by controlling the position of single electrons [1][2][8]. The fundamental unit of QCA is QCA cell created with four quantum Dots positioned at the vertices of a square.[1] [8]. The electrons are quantum mechanical particles, they are able to tunnel between the dots in a cell. The electrons in the cell that are placed adjacent to each other will interact; as a result the polarization of one cell will be directly affected by the polarization of its neighboring cells. Fig 1 below shows quantum cells with electrons occupying opposite vertices.

[FIGURE 1 OMITTED]

This interaction forces between the neighboring cells able to synchronize their polarization. Therefore an array of QCA cells acts as wire and is able to transmit information from one end to another [5][6]. Thus the information is coded in terms of polarization of cell. Polarization of each cell depends on polarization of its neighboring cells. Experimental demonstration of the QCA circuits are given in detail in [11,12,13]

Quantum Computation

To perform logic computing, we require universally a complete logic set. We need a set of Boolean logic gates that can perform AND, OR, NOT and FANIN and FAN OUT [7] Operations. The combination of these is considered as universal because any general Boolean function can be implemented with the combination of these logic primitives. The fundamental method for computing is majority gate or majority voter method [1] [3]. Suppose three inputs are given to QCA circuit, then the output of the QCA structure is tabulated in table 1.

The majority gate produces an output that reflects the majority of the inputs. The majority function is a part of a larger group of functions called threshold functions. Threshold functions works according to inputs that reaches certain threshold before output is asserted. The majority function is most fundamental logic gate in QCA circuits. In order to create an AND gate we simply fix one of the majority gate input to 0 (P = -1). To create OR gate we fix one of inputs to 1 P = +1. The inverter or NOT gate is also simple to implement using QCA. If we place two cells at 45 degrees with respect to each other such that they interact inversely.

[FIGURE 2 OMITTED]

The output of majority AND gate reflects the majority of the inputs. Suppose input A =1, B = 1, Control input 0(-1), the output is equal to 1.

[FIGURE 3 OMITTED]

The majority AND and OR gate are shown in Figure 2 and 3. Control input to AND gate is -1 and for OR gate is +1. A set of universal quantum logic gates like C-Not, Xor gates and Toffoli gates can be constructed using QCA technology; the details about these gates are given in [9]. QCA can be used as reversible, irreversible and partially reversible logic. C.S.Lent etal [10] proposed QCA clocking cells with partially reversible and irreversible logic; they estimated power dissipation and energy of QCA cells. This paper presents a quantum dot cellular automata complex gate composed of 3 input and 7 input majority gates to represent complex logic gates. We also developed fixed QCA circuit which can be used to get all Boolean logic functions and also to build combinational circuits such as comparators, parity generators and checkers. we have simulated using QCAdesigner tool [15].Finally we have constructed sum of product and product of sum representation using QCA fixed structure.

2-Input Complex gates

The fundamental logic structure of QCA is the 3-input majority gate. Previous complex gates [14] requires more than one device and implemented with only two functions. Here we have developed two input logic gates with its inversion also being available for evaluating more combinational functions. Figure 4 shows the layout representation of QCA logic structure with four input, three control gates and one output. This gate is composed of three input majority gates.

[FIGURE 4 OMITTED]

Control inputs are used to compute the output using majority voting method. The structure has four inputs (two inputs and their inversion) and one output, figure 5 shows the QCA structure constructed using QCAdesigner tool, the main advantage of QCA technology is availability of inputs and their inversion simultaneously (90[degrees] and 45[degrees] rotation of cell in a single QCA wire) hence simple two input majority gate being constructed with control inputs +1 and -1. Table 2 shows the And, Or, Nand and Nor implementation using QCA structure by majority voting scheme shown in figure 5. Let a,b,a' and b' be the inputs to QCA circuit, c1,c2 and c3 are control inputs and y be the output, from table 2 we prove single circuit used to compute all Boolean logic functions. Figure 6,7,8 and 9 shows the simulated waveforms for QCA circuit in figure 5.

[FIGURE 5 OMITTED]

[FIGURE 6 OMITTED]

[FIGURE 7 OMITTED]

[FIGURE 8 OMITTED]

When control inputs to the QCA circuit is 010, then QCA circuit functions as NOR gate, figure 6 shows the simulated waveform of NOR logic. If the control input changed to 101, circuit acts as Nand logic and if the inputs a and b are made 0, then two input AND and OR gate logic can evaluated. Figure 8 and 9 shows the simulated waveforms for AND and OR logic. As per QCA technology the gates are three nature. We will discuss in the next section multi input complex gates and X-or and X-nor logic.

[FIGURE 9 OMITTED]

Four input and Multi input gates

QCA circuit used in section II is used here to explain X-or and X-nor logic. Figure 10 shows the QCA circuit with two inputs (a,b--inversion a',b'), three control lines and one output. Only difference between figure 5 and 10 is interchange of inputs and one of the control input c2 placed at middle gate, as well as output is from the middle gate. The output Y is evaluated at clock 1. Inputs are divided such that inverted inputs a' and b' forms right side majority gate with clock 0 and a,b is at left side majority gate with clock 0.

[FIGURE 10 OMITTED]

When the control input c1 =1, c2 =0 and c3 =1, circuit acts as x-or logic and when c1 = 0, c2 =1 and c3=0 circuit acts as x -nor logic. Figure 11 and 12 shows the simulated waveforms for x-or and x-nor logic. We can note down the same structure can be used to get all Boolean logic functions and also the no of inputs can be increased to get desired logic. Table 3 shows the X-or, X-nor, And and Or logic for the figure 10.

[FIGURE 11 OMITTED]

[FIGURE 12 OMITTED]

As per table 3, when the inputs a' and b' are made zero then output y gives AND logic, when a' and b' are active high 1, then output Y gives OR logic. The advantage of the circuit considered in figure 10 is two different majority gates evaluated independently and the middle gate is used to get the output, there by reducing the one majority gate evaluation time and also separate clock being applied tot the middle output gate and hence the error (unploarization state of electron) due to clocking being reduced. Figure 13 shows the multi input complex gate. Three of the inputs to the gate are e,f and g as control inputs remaining a,b,c, and d are the inputs. Control inputs are used to specify the functionality of the circuit and remaining four inputs are used to implement Boolean function of four variables. The functionality of this gate for all configurations has been simulated using QCAdesigner tool.

[FIGURE 13 OMITTED]

The seven input gate of figure 13 can be used to form a 4 -input and 5 -input logic gates. If three of the inputs say e,f and g to have fixed polarity that is control input 1(0), output y gives AND logic (abcd). Similarly figure 13 can be used to form 4 -input OR (a + b+ c+d) gate when e,f and g to have fixed polarity of +1. In general when e =1,f =0 and g=1, sum of products for four input gate say (a+b) (c+d) cane be obtained and when e = 0, f=1 and g=0, product of sum expression (ab + cd ) can be presented. Table 4 shows the control inputs and corresponding output function for 4 input QCA gates.

It is also possible to construct 5 input complex gates, when f and g being fixed to 1 or 0. Figure 14 shows the simulated waveform of AND logic of 5 input QCA structure of figure 13 when f and g are made 0. If we compare QCA structure in figure 5, 10 and 13 we have used same structure with difference in way of feeding input and control input. Moreover multiple inputs can be used to get the desired Boolean logic, hence simulated waveforms shows same structure can be used to fit in FPGA, PLD and ASIC to get desired function.

[FIGURE 14 OMITTED]

We will discuss in the next session the use of QCA structure to form simple combinational circuits.

Combinational QCA structure

QCA structure defined in figure 5, 10 and 13 can be used to build combinational and sequential circuits. We have considered here two bit comparator, parity generator and checker circuit for the explanation purpose. Figure 15, shows QCA comparator, 16 shows the parity generator and 17 parity checker circuit. Two bit comparator has inputs (a0, a1, b0 and b1), two QCA circuits discussed as in section 2 and3, and one output as shown in figure 15. At clock 0 inputs are available for comparator; clock 1 is used to carry information for majority gate, clokc2 and 3 for evaluating the majority logic. Finally the output y (Or of two fixed QCA structure) is obtained at clock 1. Two fixed QCA structure gives xor function by setting control input as 010, both the output of Xor logic is added to get output y. Next circuit we have considered here parity generator QCAcircuit, combination of x-or and x -nor structure. Figure 17 and 18 shows the QCA parity generator circuit and simulated waveform. Control input of 010 and 101 to form combination of x-or and x-nor circuit, Let a and b be the input to xor which gives y1 output of a xor b and y1 given input to x-nor gate as y1 x-nor c to get output yout. Clock 0 and 1 is used to evaluate majority logic in fixed QCA structure, clock 2 and 3 is used to carry x-or output to x-nor gate and for inversion purpose. The output Yout is evaluated at clock2.

[FIGURE 15 OMITTED]

[FIGURE 16 OMITTED]

[FIGURE 17 OMITTED]

[FIGURE 18 OMITTED]

Conclusion

We have constructed here a simple QCA ladder type circuit which can be used to get all types of Boolean logic functions thereby used as fixed module in FPGA and ASIC applications.

Multi level inputs (three, four and five) are used to get desire Boolean logic that can be used to construct complex gates in QCA technology. We also proved by constructing combinational circuit with the same QCA circuit as comparotr and parity generator.

Further we can test these structure for different sequential QCA circuits by varying the clock zones

QCA is one of the upcoming nanotechnology, construction of these circuits and simulated waveforms will give further improvements in building QCA digital circuits.

Reference

[1] K.Walus, Wei Wang and Julliaen et al, December 2004. "Majority logic reduction for Quantum Cellular Automata" in Proc IEEE Nanotechnology conf, vol 3 pp 341-350

[2] K.Walus, Wei Wang and Julliaen et al, December 2004. "Quantum Cellular Automata adders" in Proc IEEE Nanotechnology conf, vol 3 page 461-463.

[3] K.Walus, Schulaf and Julliaen et al, 2004 "High level Exploration of Quantum Dot Automata" in Proc IEEE. Nanotechnology conf, vol 2, page 30-33

[4] K.Walus, Schulaf and Julliaen et al, 2004. "Circuit design based on majority gates for application with Quantum dot cellular automata" in Proc IEEE Nanotechnology conf, vol 4, page 1350-1354.

[5] K.Walus, Dimitrov and Julliaen et al, 2003 "Computer Architecture structure for Quantum Cellular Automata"in Proc IEEE Nanotechnology conf, vol 3, page 1435-1439.

[6] K.Walus, Dysart and Julliaen et al, June 2004. "QCQ Designer A Rapid design and simulation tool for quantuim dot cellular automata" in IEEE transactions on Nanotechnology conf, vol 3, No-2

[7] K.Walus, Dysart and Julliaen et al, March 2004 "Split current Quantum dot cellular automata modeling and simulation " in IEEE transactions on Nanotechnology conf, vol 3.

[8] A.Vetteth et al., 2002. "Quantum dot cellular automata carry-look-ahead adder and barrel shifter," in Proc. IEEE Emerging Telecommunications Technologies Conf.

[9] C.S. Lent and P. D. Tougaw, 1997 "A device architecture for computing with quantum dots," Proc. IEEE, vol. 85, no. 4, pp. 541-557.

[10] C.S. Lent and P. D. Tougaw, 2002 "A partially reversible gate logic for quantum cellular automata technology," Proc. IEEE, vol. 12, no. 4, pp. 541-557.

[11] A.Orlov et al., 2000"Experimental demonstration of clocked single-electron switching in quantum-dot cellular automata," Appl. Phys. Lett., vol. 77, no. 2, pp. 295-297.

[12] A.Orlov et al., 1999 "Experimental demonstration of a binary wire for quantum-dot cellular automata," Appl. Phys. Lett., vol. 74, no. 19, pp 2875-2894

[13] I.Amlani et al.,2000 "Experimental demonstration of a leadless quantum-dot cellular automata cell," Appl. Phys. Lett., vol. 77, no. 5, pp. 738-740.

[14] P.D. Tougaw and C. S. Lent, 1994 "Logical devices implemented using quantum cellular automata," J. Appl. Phys., vol. 75, no. 3, pp. 1818-1825.

[15] www.qcadesigner.ca

E.N. Ganesh (1), Lal Kishore (2) and M.J.S. Rangachar (3)

(1) Research scholar JNT, Hyderabad, Andhra Pradesh, India

(2) Registrar JNTU, Hyderabad, Andhra Pradesh, India

(3) HOD /ECE Dept BSA Crescent Engg College, Andhra Pradesh, India
Table 1: Majority voting scheme [4] [5]

INPUT   OUTPUT MAJORITY
        VOTING
000     0
001     0
010     0
011     1
100     0
101     1
110     1
111     1

Table 2: Functional output of QCA structure for various
values of control inputs of figure 5

b    a    C1   Y1   C2   a'   Y2   C3   b'   Y
                                             output
          0         1              0         Nor
0    0    0    0    1    1    1    0    1    1
0    1    0    0    1    0    0    0    1    0
1    0    0    0    1    1    1    0    0    0
1    1    0    1    1    0    1    0    0    0
          1         0              1         Nand
0    0    1    0    0    1    0    1    1    1
0    1    1    1    0    0    0    1    1    1
1    0    1    1    0    1    1    1    0    1
1    1    1    1    0    0    0    1    0    0
          0         1    x         0    y    And
                                             x.y
0    0    0    0    1    0    0    0    0    0
0    0    0    0    1    0    0    0    1    0
0    0    0    0    1    1    1    0    0    0
0    0    0    0    1    1    1    0    1    1
          0              1    x    1    y    or
0    0    0    0    1    0    0    1    0    0
0    0    0    0    1    0    0    1    1    1
0    0    0    0    1    1    1    1    0    1
0    0    0    0    1    1    1    1    1    1

Table 3: Functional output of QCA structure for various
values of control inputs of figure 10

b    a    C1   Y1   C2   Y3       Y2   C3   b'   a'
                         output
          0         1    X-nor         0
0    0    0    0    1    1        1    0    1    1
0    1    0    0    1    0        0    0    1    0
1    0    0    0    1    0        0    0    0    1
1    1    0    1    1    1        0    0    0    0
          1         0    X-or          1
0    0    1    0    0    0        1    1    1    1
0    1    1    1    0    1        1    1    1    0
1    0    1    1    0    1        1    1    0    1
1    1    1    1    0    0        0    1    0    0
                         AND
0    0    0    0    1    0        0    0    0    0
0    1    0    0    1    0        0    0    0    0
1    0    0    0    1    0        0    0    0    0
1    1    0    1    1    1        0    0    0    0
                         OR
0    0    1    0    0    0        1    1    1    1
0    1    1    1    0    1        1    1    1    1
1    0    1    1    0    1        1    1    1    1
1    1    1    1    0    1        1    1    1    1

Table 4: Control inputs and output functions
for structure in figure 13.

e   f   g   Y
            Output function
0   0   0   abcd
0   0   1   ab(c+d)
0   1   0   ab +cd
0   1   1   ab + (c+d)
1   0   0   (a+b) cd
1   0   1   (a+b) (c+d)
1   1   0   (a+b) + cd
1   1   1   a + b + c + d
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Author:Ganesh, E.N.; Kishore, Lal; Rangachar, M.J.S.
Publication:International Journal of Applied Engineering Research
Article Type:Report
Geographic Code:1USA
Date:Mar 1, 2008
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