Stretch chip embeds programmable logic within the processor.
Stretch, Inc. has announced the S5000 family of software-configurable processors that are designed to combine the best of general-purpose processors and the parallelism and flexibility of FPGAs. The company also offers a suite of tools that enable developers to automatically configure and optimize the processor using their C/C++ code. Every S5000 is powered by the Stretch[TM] S5 engine, which incorporates the Tensilica Xtensa[R] RISC processor core and the company's Instruction Set Extension Fabric (ISEF). The ISEF is a software-configurable data-path based on proprietary programmable logic. Using the ISEF, system designers extend the processor instruction set and define the new instructions using their C/C++ code. The S5 engine addresses major RISC bottlenecks to provide high performance. Unlike typical RISC processors' ALUs that perform low-level operations such as shift, add and multiply, the ISEF can execute thousands of operations as a single instruction. The device addresses the data compute bandwidth bottlenecks by using thirty-two 128-bit-wide registers couple with 128-bit-wide access to memory to feed data to the ISEF at a high bandwidth. Other features include a 300 MHz, 32-bit Xtensa-based processor; 16- and 24-bit instructions; FPU; MMU with TLB; user-defined extensions to the core ISA; low power consumption; and support for standard operating systems. The processor family debuts with three members, all based on the S6 engine. The products differ only in their I/O and packaging. Stretch, Inc.
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|Publication:||ECN-Electronic Component News|
|Date:||May 1, 2004|
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