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Stress plagues the fastest chips.

Stress Plagues the Fastest Chips

It first came to light about five years ago. An insidious plague was killing integrated-circuit chips as they sat in storage. Defects -- some as serious as the severing of metal circuit lines -- were developing under normal storage conditions, sometimes without a chip ever having been used. Last week, Cornell University materials scientists published the first complete theory that explains on an atomic scale what is causing these chips to fail. The silent killer, the researchers say, is unrelieved stress.

Computer chips are fabricated at temperatures of about 400[deg]C. The current chip-making process bonds aluminum-based, current-carrying circuit lines onto a substrate, usually silicon. As the finished chip cools to room temperature, its metal circuit lines attempt to contract. However, because they are anchored to a more massive base with a smaller thermal expansion/contraction rate, the lines never fully contract. Their unrelieved "desire" to shrink further creates a materials stress in the metal lines, according to the theory.

The first sign of this stress is the formation of voids -- a cluster of several empty atomic sites -- in the lattice structure of the lines' metal. They develop in the "boundary region" between metal grains (single crystals). As the metal attempts to further relieve its stress, layers of atoms begin peeling off around these voids and redepositing nearby. As more and more atoms leave, the microscopic voids at the grain boundaries grow into cavities.

"This is a thermally activated phenomenon," explains Che-Yu Li, who heads the research team. "At higher temperatures, it can happen within a few hundred hours. At room temperature, it can take a year or two." The important thing, he emphasizes, is that this type of failure can occur without currents passing through the chip.

In today's fastest chips, the metal lines are only about 1 micron wide. They also are about one grain wide, with single grains aligned in a row. It doesn't take long for small voids in the boundaries between the grains to grow enough that line-severing cracks form. And that is one reason why the highest-performance chips -- those having the narrowest current-carrying lines -- are most vulnerable, Li says.

Though this passive-cracking phenomenon has been linked since 1984 to stresses introduced during chip fabrication, the Cornell theory, published in the July 4 APPLIED PHYSICS LETTERS, is the first to model the atomic behavior of chip lines under stress. Li says it also is the first to "predict its width dependence." Specifically, his data indicate that for each 10-fold reduction in circuit-line widths, the risk of stress-cracking failure will increase 1,000-fold.

Though their smaller size will make the next generation of chips significantly more vulnerable, current chips are already being affected. Notes Billy Livesay, a chip-reliability engineer at the Georgia Institute of Technology in Atlanta, "A particular microprocessor has had some failures in the past year that are bugging the industry: These things are cracking -- either in service or on the shelf" -- from the type of stress, he says, that Li has modeled.

In fact, the potential for stress cracking "is a well-recognized problem in the [chip] industry," says William Nix, a Stanford University materials scientist. Though engineers have been quietly tinkering with their chip-fabrication processes to solve the problem, "rarely if ever have they dealt with what the microscopic causes are," he says. That's why Nix believes the Cornell theory "is a good, solid, fundamental contribution." And its predictive capabilities, he adds, could guide engineers toward solutions to the problem.

What types of solutions? Working at Cornell's National Nanofabrication Facility, Li and his colleagues will be exploring the idea of altering metals used in the lines and developing more flexible bonds between the metal and its substrate.
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Title Annotation:semiconductor chips
Author:Raloff, Janet
Publication:Science News
Date:Jul 16, 1988
Words:618
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