Solder Void Modeling and Its Influence on Thermal Characteristics of MOSFETs in Automotive Electronics Module.
Solder voids are gas occlusions that form in solder ioints during the soldering process. The voids are caused by the amount of outgassing flux that gets entrapped inside the solder joint during reflow. Voiding is one of the major reliability concerns when solder is used as the thermal interface material. The use of lead (Pb)-free solders has increased concerns emanating from solder voids due to its poor solderability. Studies indicate that in certain Pb-free solders the occurrence of voids can be in excess of 50% of solder volume [1, 2]. The presence of voids in solders reduces the effective area available for heat transfer. This subsequently results in an increase in thermal resistance and rise in chip iunction temperature that can lead to temperature related failure mechanisms.
The void formation during manufacturing is almost inevitable due to following circumstances which are impossible to control:-
* Entrapment of gas bubbles formed by reactions among material and fluxes during reflow soldering process
* Poor wetting of solder due to contaminated or defective back side metallization of silicon die or heat spreader
* Solder-alloy fatigue due to cyclic thermo-mechanical stresses experienced during device operation
Solder voids can be classified generally in three ways (there are six groups) as listed below:-
1. Solder wetting point of view
* Shallow voids (partially wetted)
* Deep voids (completely not wetted voids)
2. Void Configuration
* Distributed small voids
* Large coalesced voids
3. Void Location
* Centre of the STIM
The various void types have different level of impact on the thermal performance of electronics packaging. The precise thermal behavior evaluation is essential for these different types of void patterns.
An extensive literature survey was carried out to understand the previous works done on solder void modeling. The surveys also aided in understanding the general trend of the void percentage level normally observed in solder joints. Three dimensional finite element modeling was explored by Chang et al.  to investigate the effect of solder void size and location on thermal resistance of power devices. The study suggested that chip temperature and thermal resistance increase with increase in void percentage. Thermal resistance has increased to 6.5% and 27.2% for void percentage of 20% and 79% respectively. Fleischer et al.  used experimental and numerical methods to predict the relation between void geometry and package resistance. Thermal resistance has increased to 30% with 73% of random voids. But for contiguous voids of 73%, thermal resistance increased up to 200%. Two dimensional FEA is used by Zhu  to study thermal impact of voids on power device. The chip area is around 0.5mm X 0.5mm having power dissipation of 1W. Thermal impedance variation with different classes of voids and void percentage is also highlighted in his work. The result indicated that impact on thermal resistance is greater for larger, coalesced and edge voids compared to small distributed voids. Biswal et al.  assessed the impact of solder voids on the silicon die temperature during transient operations of a high power automotive electronic module. The solder voids were modeled explicitly using ANSYS [R]. It is shown that there is profound impact of solder voids on the silicon die temperature depending on the size and void fraction. But the void distribution seems to have negligible impact on the die temperature. Katsis et al.  demonstrated that operation of power semiconductor devices induces thermal stresses resulting in void growth. Commercially available TO-247 style MOSFETs were power cycled, imaged and thermally analyzed to generate a correlation between void percentage and thermal impedance. The void percentage has increased from 10% to 35% for 4000 cycles. Liu Chen et al. , performed analysis using ANSYS [R] to model D2PAK package and calculated 'Rjc' for different types of randomly distributed voids using statistical approach. Four different void configurations viz. upper voids, middle voids, bottom voids and through thickness voids are analyzed. The increase in thermal resistance was highest at around 67% for through thickness voids. The upper voids, middle voids and bottom voids experienced the increase in resistance of 62%, 60% and 56% respectively.
The literature survey indicated that void size, void location and void percentage cannot be generalized for all devices and it can vary drastically for the same device during mass manufacturing. The void distribution seems to have less impact on the rise in chip temperature. This means that explicitly modeling the voids may not be essential to capture the real effects. Most of the solder void studies done are in the die-attach regions. It was also noted that through thickness voids has maximum thermal resistance compared to upper voids, middle voids and bottom voids. Hence the current study is focused on solder between the device and the PCB interface regions for through thickness voids. In the present work, different numerical models are attempted to study the void impact by using single and equally distributed void patterns matching the percentage void fraction to replace the time consuming explicit void modeling.
SOLDER VOIDS IN MOSFET
The studies are performed on a MOSFET device (power package with exposed pad) that is very commonly used in automotive electronic modules. The MOSFET has resistance junction to case of 2[degrees]C /W and its allowable maximum power dissipation for the present application can vary up to 12W. MOSFET X-ray image with 20% void fraction is shown in figure 1.
For the present study void percentage range is chosen based on the the solder X-ray images taken for a series of MOSFET. X-ray images indicated that the maximum solder void percentage is around 50% with different sizes of voids. Figure 2a and 2b shows the solder voids extracted from the X-ray images for 20% and 50% void percentage. For each percentage of voids, two different configurations that are commonly found are chosen. One configuration is corresponding to small distributed voids and other one is large coalesced voids. In the smaller voids, the diameter of voids varies from 0.05mm to 1mm and for bigger voids the sizes greater than 1mm diameter is present.
BASELINE THERMAL MODEL
Initially to understand the effect of solder void on MOSFET temperatures, steady state thermal analysis is carried out using commercial CAE software package FloTHERM [R] without solder voids. The thermal model used for simulation is shown in figure 3. This model is used as baseline to compare the temperature increase due to void presence. The internal construction of MOSFET thermal model is shown in figure 4. The baseline thermal model consists of MOSFET mounted at center of PCB of dimension 60mm x 60mm surrounded by ambient air. The solder thickness considered in simulation is 0.1mm. MOSFET device has 22 thermal via underneath the device. Thermal via effect is taken in analysis by appropriately calculating the orthotropic properties. The thermal model developed captured all three modes of heat transfer viz. conduction, convection and radiation. To account for radiation appropriate emissivity properties are applied to the components. PCB and Encapsulant emissivity is assumed to be 0.8. The dimensions of the different components of the thermal model are given in table 1. The thermal conductivity material properties used are given in table 2.
The thermal contours of baseline model with 6W power dissipation for 25[degrees]C ambient temperature is shown in figure 5.
DETAIL SOLDER VOID MODEL
From the X-ray images of the solder, it is found that in general, void percentage can vary to a maximum of around 50%. In a detailed solder void model, the voids are explicitly modeled replicating the X-ray images. Thermal analysis is carried out for two different void percentages 20% and 50%. For each solder void percentage, studies are carried out for two void configurations viz. small and big. The void configurations studied are shown in figure 2a and 2b. Thermal studies are carried out using model shown in figure 3. Table 3 provides the consolidated summary of MOSFET temperature rise over ambient for varying power dissipation values (2W to 12W). The simulation results indicated that 20% solder void does not have significant temperature raise compared to that of 'No void' situation i.e. 0.1[degrees]C to 0.7[degrees]C. But for 50% void case, considerable rise in temperature is noted as the power increases. The temperature deviation from 'No void' is around 1[degrees]C to 9[degrees]C. It is seen that bigger void configuration causes more resistance to heat flow and causes the MOSFET temperature to rise than that of small void configuration (same as observed by many researchers as discussed in literature survey section). To have a conservative estimate of the temperature rise because of solder voids, it is always better to consider bigger void configuration. Therefore to develop simplified numerical model for predicting the void effect, the model having bigger voids with 50% void fraction and 20% void fraction is chosen for the study.
NUMERICAL VOID APPROACH
Detailed solder void modeling requires a higher preprocessing and solving time, due to a need for capturing intricate details leading to higher mesh count. In an electronic module with a PCB, the power package (MOSFET) that is of importance can be present in multiple numbers. The solder void pattern will vary drastically for each of these MOSFETs. During mass manufacturing, the PCB is produced in millions and void distribution, shape and size can vary drastically. Considering this scenario, it is not practical to develop a detailed solder void model for each MOSFET. To avoid this time consuming effort, different numerical void patterns are attempted.
Different numerical void patterns like single void and distributed void concept are explored (refer figure 6). The void shapes are assumed to be of circular shape. In distributed void patterns, 2 X 2, 3 X 3 and 4 X 4 configurations are studied. The void diameter for each pattern is derived such that the percentage void fraction matches to that of void patterns extracted from X-ray images (20% void and 50% void). Studies are carried out for a power dissipation ranging from 2W to 12W for all the numerical void patterns and results are compared to that of detailed solder void model in table 4.
From the results it can be seen that, the single void approximation deviates around 1.2% to 2.6 % compared to the detailed void model depending on power number. In distributed void concept, the deviation is found to be less compared to single void approach. The 2 X 2 void patterns have a deviation of around 0.2% to 2.3%. In case of 3X3 and 4 X 4 patterns, the maximum deviation is found to be 1%. This suggests that either 3 X 3 or 4 X 4 numerical void patterns can be used to replicate the detailed solder void. The 3 X 3 void patterns require less effort in comparison to 4 X 4 void patterns. Hence 3 X 3 numerical void pattern is used as a representative model that can replace the detailed solder void model.
The simulation time taken for 50% void scenario with small voids (figure 2b) is around 85 minutes. For same solder void percentage with 3 X 3 circular patterns took 45 minutes.
VOID SHAPE SENSITIVITY
All the numerical models studied earlier used circular shaped voids. In order to study the effect of void shape on device temperature, circular voids are replaced with square voids. The comparison of results between circular voids and squared voids is shown in table 5. The temperature predicted using square voids are conservative and deviates around 0.9%-1.6% from circular voids. This conveys that void shape have negligible impact on device temperature for the MOSFET being studied.
RISK ASSESSMENT OF VOIDS
To decide the acceptance or rejection criteria for MOSFET under study, it is essential to understand the expected increase in device temperature as a function of percentage void fraction. The percentage void fraction for which the device temperature is not exceeding the maximum allowable limit can be accepted and rejected elsewise. But different MOSFETs in the same module can also have varying power dissipation depending on the functional requirement. Therefore the acceptance criterion is a function of void percentage and power dissipation. Earlier study, indicated that square voids provide conservative estimate and negligible impact on device temperature. As a result, for establishing the guideline, studies are conducted using 3 x 3 square voids for varying void percentage and power dissipation. The percentage variation of void is captured in the model by varying the size of the square hole as shown in figure 7.
Simulation studies are carried out for the power dissipation of the MOSFET ranging from 2W to 12W (for model refer figure 3). The guideline set for the increase in temperature levels with reference to 'No void' scenario is given in table 6. Table 6 also expresses color codes based on range of temperature increase for identifying risks. The color code is used to identify the risks with ease.
The graphical plot shown in figure 8 summarizes the results for the entire range of study. The solder void percentage of 20% seems to have no concern till 4W and has low risk for the maximum rated dissipation of 12W and hence can be accepted. But when the void percentage increases above 20 %, risk assessment should be made according to the guidelines provided based on color coded figure.
In general, automotive electronic modules have an enclosure that shields electronics from the external harsh environments. The enclosure does not allow the devices mounted on PCB, to interact with the external ambient air directly. As a result, the temperature results for studies with and without enclosure will be completely different. When the module operates, the heat generated from the devices raises the temperature of the air entrapped inside the enclosure. To capture this effect, analysis is repeated by including enclosure in the model. The enclosure thickness is considered as 2 mm. Enclosures are placed such that there is about 10mm gap between the basic model components and the enclosure walls on all sides. Two types of enclosure viz. plastic and steel that are commonly used in automotive electronics are explored.
1. Plastic enclosure (Conductivity 0.2 W/m K; emissivity 0.8)
2. Steel enclosure (Conductivity 65 W/m K; emissivity 0.65)
Figure 9 shows the results of adding an enclosure to the model. It is found that the results of having enclosure either of plastic or steel makes no difference in results. Hence the results shown in figure 9 are valid for both plastic and steel enclosure. The void effect in device temperature rise is predominant for model with enclosure than without enclosure. For example, 40% void with power of 10W is of moderate risk without modeling enclosure, but is at higher risk with enclosure. The same trend is visible through out for all the percentage void scenarios. As most of automotive electronics deal with modules with completely sealed enclosure, the study with enclosure is of more practical relevance.
The device temperature and thermal resistance increases with increase in void size and void fraction. Hence it is essential to understand the solder void effect in relation with device temperature for deciding the acceptance or rejection criteria. Initially detailed solder void model is generated replicating the X-ray images taken for MOSFET that are commonly used in automotive electronics. X-ray images showed voids ranging up to maximum of 50%. Simulation studies are performed using detailed model of solder voids to estimate the temperature rise from 'No void' scenario. The detailed solder models pose difficulty in modeling because it consumes lot of time for creating the model and increased solver time due to higher mesh count. Hence studies are carried out for arriving at a simplified numerical model that can predict the results with reasonable accuracy. The void patterns of different types are studied and the 3 x 3 numerical void patterns found to produce temperature rise close to that of detailed model.
In mass production, it is always beneficial to have a guideline to assess the risk of solder void. The acceptable void percentage should be decided such that the device temperature rise is within allowable limits. Several studies carried out for varying power dissipation and void percentage, assisted in finalizing the acceptance levels.
Later to include the electronic module effect, thermal analysis is carried out with enclosure. Two different commonly used enclosure materials viz. plastic and steel are used for the analysis. It was noted that the thermal impact due to void presence is predominant with enclosure than without it. Then risk assessment criteria are summarized based on the temperature rise for MOSFET device for with and without enclosure. The solder did not pose any temperature rise concern for MOSFET even for maximum power rating of 12W, when void percentage is within 20%. For the solder having voids above 20 %, the decisions should be taken based on the risk assessment graphs.
[1.] Chan, Y.C., Xie, D.J., and Lai, J.K.L, "Experimental Studies of Pore Formation in Surface Mount Solder Joints," Mater. Sci. Eng. 1996; 38:53-61.
[2.] Zeng, K., and Tu, K.N., "Six Cases of Reliability Study of Pb-Free Solder Joints in Electronics Packaging," Mater. Sci. Eng. 2002; 38:55-105.
[3.] Chang, J., Wang, L., Dirk, J., and Xie, X., "Finite Element Modeling Predicts the Effects of Voids on Thermal Shock Reliability and Thermal Resistance of Power Device," Weld. J. 2006; 85:63s-70s.
[4.] Fleischer Amy, S., Chang Li-hsin, and Johnson Barry, C., "The Effect of Die-Attach Voiding on the Thermal Resistance of Chip Level Packages," Microelectron. Reliab. 2006; 46:794-804.
[5.] Zhu, N., "Thermal Impact of Solder Voids in the Electronics Packaging of Power Devices, " Semiconductor Thermal Measurement and Management Symposium, IEEE,2002.p.22-29.
[6.] Biswal Laxmidhar, Krishna Arvind and Sprunger Doug, "Effect of Solder Voids on Thermal Performance of High Power Electronic Module," Electronics Packaging Technology Conference IEEE; 2005, p.526-531.
[7.] Katsis, D.C., and vanWyk, J.D., "A Thermal Mechanical and Electrical Study of Voiding in the Solder Die-Attach of Power MOSFETs, "IEEE Transactions on Components and Packaging Technologies, Volume: 29, Issue:1, March 2006; p.127-136.
[8.] Liu Chen, Mervi Paulasto-Krockel, Ulrich Frohler, Dirk Schweitzer and Heinz Pape, "Thermal Impact of Radomly Distributed Solder Voids on Rth-JC of MOSFETs, "2nd Electronics System Integration Technology Conference IEEE;2008, p.237-243.
Kesav Kumar Sridharan, Technical Leader for Digital Validation, Hardware Engineering at Delphi Technical Center India holds a Master's degree in Aeronautical Engineering and has around 15 years of industry and research experience. Before to Delphi he was with GE-India Technology Center and also with ISRO for 7 years. His expertise includes thermal analysis, experimental heat transfer and thermo-physical properties evaluation. He has published several papers in international and national conferences organized by AIAA, SAE, IEEE, ASME and ISHMT.
Swaminathan Viswanthan, Advanced Technical Leader for Digital Validation, Hardware Engineering at Delphi has done his PhD in heat transfer. He is having around 15+ years of experience in the field of heat transfer and associated with Delphi for around 10 years. He has published several papers in international and national Journals/conferences.
Pb - Lead
FET - Field Effect Transistor
CAE - Computer Aided Engineering
STEM - Solder Thermal Interface Material
FEA - Finite Element Analysis
Rjc - Resistance junction to case
PCB - Printed Circuit Board
Kesav Kumar Sridharan and Swaminathan Viswanathan
Delphi Automotive Systems
Table 1. Dimensions of FloTHERM [R] model Component Dimension PCB 60.0mm X 60.0mm X 1.60mm Encapsulant 6.54mm X 6.54mm X 2.29mm Die flag 5.40mm X 5.40mm X 0.67mm Die 2.00mm X 2.00mm X 0.30mm Thermal via 8.86mm X 9.42mm X 1.60mm Solder in FET-PCB interface 5.40mm X 5.40mm X 0.10mm Solder in Leads 1.52mm x 0.76mm x 0 10mm Table 2. Thermal conductivity properties Component Thermal Conductivity, W/ m K PCB In-plane: 61.5; Out-Plane: 0.38 Encapsulant 0.65 Die flag 301.5 Die 117.5 Thermal via In-plane: 61.5; Out-Plane: 6.54 Solder in FET-PCB interface 38 Leads 385 Table 3a. Comparison of temperature rise between with and without void Temperature Rise from Ambient in [degrees]C Power, W No void 20% void 50% void Small Big Small Big 2 30.1 30.2 30.2 31.6 31.5 6 85.1 85.2 85.2 87.5 90.0 12 163.3 163.9 164.0 168.9 172.2 Table 3b. Percentage deviation of temperature between with and without void Power, W % Deviation from No Solder Void 20% void 50% void Small Big Small Big 2 03 0.3 3.6 3.6 6 0.1 0.1 2.8 5.8 12 0.4 0.4 3.4 5.4 Table 4a. Comparison of temperature rise of numerical void models against the detail void model Cases Temperature Rise from Ambient in [degrees]C Single void 2X2 pattern 3X3 pattern 4X4 pattern 2W: 50% void 32.2 32.2 31.7 31.7 6W; 50% void 91.1 89.4 89.5 89.5 12W: 50% void 176.7 173.4 173.7 173.8 2W; 20% void 30.8 31.0 30.6 30.4 6W; 20% void 86.8 85.7 86.0 85.5 12W; 20% void 166.1 164.4 164.7 164.9 Cases Detail Model 2W: 50% void 31.5 6W; 50% void 90.0 12W: 50% void 172.2 2W; 20% void 30.3 6W; 20% void 85.2 12W; 20% void 164.0 Table 4b. Percentage deviation of temperature between numerical void and detail void model Cases % Deviation from Detail Model Single void 2X2 pattern 3X3 pattern 4X4 pattern 2W; 50% void 2 2 2 2 0.6 0.6 6W; 50% void 1.2 0.7 0.6 0.6 12W; 50% void 2.6 0.7 0.9 0.9 2W; 20% void 1.7 2.3 1.0 0.3 6W; 20% void 1.9 0 6 0.9 0.4 12W; 20% void 1.3 0.2 0.4 0.5 Table 5. Circular and square voids results (3 X3 pattern, 50% voids) Power, W Temperature Rise from Ambieot in [degrees]C % Deviation Circle Square 2 31.7 32 2 1.6 4 61.1 62.0 1.5 6 89.5 90.6 1.2 8 117.4 118.7 1.1 10 145.3 146.6 0.9 12 173.7 175.2 0.9 Table 6. Guideline corresponding to temperature increase compared to 'No void' case Temperature increase Guideline compared to 'No void' < 1 [degrees]C No Concern 1 [degrees]C to 2 [degrees]C Very Low Risk 2 [degrees]C to 4 [degrees]C Low Risk 4 [degrees]C to 6 [degrees]C Moderate Risk > 6 [degrees]C High Risk
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|Author:||Sridharan, Kesav Kumar; Viswanathan, Swaminathan|
|Publication:||SAE International Journal of Passenger Cars - Electronic and Electrical Systems|
|Date:||Aug 1, 2017|
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