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Simulation and implementation of active neutral point clamped multilevel inverter powered by PV source.


Among the different renewable-energy sources, solar energy has been one of the most active research areas in the past decades, both for grid-connected and stand-alone applications. The benefits of power generation from these sources are widely accepted. They are essentially inexhaustible and environmentally friendly.

This paper a three-level three-phase active neutral point clamped multilevel inverter powered by PV source. Multilevel inverters offer several advantages compared with their conventional voltage source inverter. It is used to synthesize a desired AC voltage from several levels of DC voltages. As the number of level increases the harmonic content decreases significantly thus reducing the filter requirements. The diode clamped multilevel inverters share the same DC level for each of the three phases which decreases dc cabling and losses on the dc side (Sergio et al 2008, Vassillios et al 2007, Martina Calais 2000). It has gained more interest because of its advantages over other MLI configurations. This paper focuses on a three-phase active neutral point clamped multilevel inverter which solves the unbalanced power loss distribution among the devices that occurs in the conventional diode clamped multilevel inverter. The proposed inverter offers advantages such as the possibility of lower switching frequency and lower electromagnetic interference (Jeyraj et al 2009, F. S. Kang et al 2005, Salmi et al 2012).

A multicarrier phase disposition PWM technique is employed for the proposed active neutral point clamped multilevel inverter to reduce the harmonics and the performances of the active neutral point clamped multilevel inverter allows extracting maximum power and reduce the output-voltage harmonic distortion. The block diagram is shown in Figure. 1. MATLAB/SIMULINK is used for the implementation of the active neutral point clamped multilevel inverter and gate pulse generation is implemented using FPGA. The simulation results are verified experimentally.


Modelling of Solar Cell:

Each solar cell is the building block of a photovoltaic panel. A photovoltaic panel is developed by connecting many solar cells in series and parallel. A single solar cell can be modeled by utilizing current source, diode and two resistors as shown in Figure 2.


The equation for a solar cell is given by

I = [I.sub.lg] - [I.sub.os] * [exp{q * [V + 1 * [R.sub.s]]/[A * k * T]} - 1] - [V + 1 * [[R.sub.s]]/[]] (1)

[I.sub.os] = [I.sub.or] * [(T/[T.sub.r]).sup.3] * [exp{q * [E.sub.go] * [[1/[T.sub.r]] - [1/T]]/[A * k]}] (2)

[I.sub.lg] = {[I.sub.scr] + [K.sub.i] * (T - 25)} * [delta]

I = [N.sub.p] * [I.sub.lg] - [N.sub.p] * [I.sub.os] * [exp{q * [[V/[N.sub.s]] + 1 * [[R.sub.s]/[N.sub.p]]]/[A * k * T]} - 1] - [[V * ([N.sub.p]/[N.sub.s]) + 1 * [R.sub.s]]/[]]

Where I & V: Solar cell output current and voltage;

[I.sub.os]: Solar cell reverses saturation current;

T: Solar cell temperature in Celsius;

k: Boltzmann's constant, 1.38 * [10.sup.-19] J/K;

q: Electron charge, 1.6 * [10.sup.-23]C;

[K.sub.i]: Short circuit current temperature coefficient at [I.sub.scr];

[lambda] : Solar cell irradiation in W/m[conjunction]2;

[I.sub.scr]: Short circuit current at 25 degree Celsius;

[I.sub.1g]: Light-generated current;

[E.sub.go]: Band gap for silicon;

A: Ideality factor;

[T.sub.r]: Reference temperature;

[I.sub.or]: Cell saturation current at Tr;

[]: Shunt resistance;

[R.sub.s]: Series resistance;

The P-V and V-I characteristics for a photovoltaic cell are given in Figures. 3 & 4. It can be seen that the photovoltaic cell operates as a constant current source at low values of operating voltages and a constant voltage source at low values of operating current. Electrical specifications of photovoltaic panel are:

Open circuit voltage: 21V

Short circuit current: 5.5A

Total no of cells in series: 36

Solar cell temperature: 30 degree Celsius



Operation of Active Neutral Point Clamped Multilevel Inverter:

A three-phase (3-level) active neutral point clamped multilevel inverter is shown in Figure.5. An m-level inverter leg requires 2(m - 1) switching devices and (m - 1)(m - 2) clamping switches. For a three-level inverter, (m = 3), it needs four switching devices and two clamping switches per leg as shown in Figure 5 (Changliang Xia et al 2011, Mona F. Moussa Sergio et al 2012, Busquets-Monge et al 2008).

1. For output voltage of [V.sub.o] = [V.sub.dc], all the upper side--half switches are turned on, i.e., [T.sub.1], [T.sub.2] and [T.sub.6] are on.

2. For output voltage of [V.sub.o] = [V.sub.dc/2], all the lower side--half switches are turned on, i.e., [T.sub.3], [T.sub.4] and [T.sub.5] are on.

3. For output voltage of [V.sub.o] = 0, only [T.sub.1], [T.sub.3], T6 are on and [T.sub.2], T5, T6 are off.


Table 1 shows the switching sequence of the proposed ANPCMLI. Switching state "1" means the switch is on condition and state "0" means the switch is off condition. It should be noticed that there are two complementary switch pairs. These pairs for single leg of the inverter switches are ([T.sub.1], [T.sub.2], [T.sub.6]) & ([T.sub.3], [T.sub.4], [T.sub.5]).Thus, if one of the complementary switch pair is turned on condition, the other of the same pair switches must be in off condition. Two switches are always turned on condition at the same time.

Analysis of Modulation Strategies For Anpcmli:

The performance of a multilevel inverter is mainly decided by the control strategies as it is related to the harmonic contents of the output voltage. There are many techniques reported for multilevel technology but this paper insists on a multicarrier Phase Disposition PWM technique [(Jin Li et al 2008, Barbosa, P et al 2005, Lucian Parvulescu et al 2011)]. There are several well-known modulation techniques as follows:

A. Single-Carrier SPWM (SCSPWM)

B. Sub-Harmonic PWM (SHPWM)

Sub-Harmonic PWM is an exclusive control strategy for MLI and has further classifications.

They are:

i. Multicarrier PWM

ii. Double carrier PWM

1) Carrier Disposition PWM method:

Phase Disposition PWM(PD):

* Alternative Phase Opposition Disposition PWM(APOD)

* Phase Opposition Disposition PWM (POD)

2) Phase Shifted Carrier PWM method (PSPWM)

Multicarrier PDPWM

In phase disposition pulse width modulation method, the PWM carriers are in phase across all the bands. For this technique, significant harmonic energy is concentrated at the carrier frequency. The multicarrier PDPWM is based on a comparison of a sinusoidal reference signal with triangular carrier signals. (m-1) carrier signals are required to generate 'm' levels. They have the same carrier amplitude [A.sub.c] and the same carrier frequency [f.sub.c]. The sine reference waveform has a reference frequency [f.sub.r] and reference amplitude [A.sub.r] (P. Palanivel et al 2011, Zhong Du et al 2009).The features of PDPWM technique are as follows:

1) Four carrier waveforms in phase are arranged.

2) The converter is switched to + Vdc/2 when the sine wave is greater than both the upper carriers.

3) The converter is switched to zero when sine wave is lower than upper carrier but higher than the lower carrier.

4) The converter is switched to--Vdc/2 when the sine wave is less than both lower carriers.

The control degree of freedom in multicarrier PWM technique are defined as Frequency modulation index

[m.sub.f] = [f.sub.c]/[f.sub.r] (5)

Amplitude modulation index

[m.sub.a] = [2/[m - 1]] * [[A.sub.r]/[A.sub.c]] (6)

The sinusoidal reference and triangular carrier waveforms are shown in Figure 6. The gating pattern for a single phase ANPCMLI using multicarrier PDPWM is shown in Figure 7.



Simulation Results:

Simulink model of the ANPCMLI powered by PV is shown in Figure.8. Table 2 shows simulation parameter for three phase ANPCMLI.





The photovoltaic panel voltage is about 21.75 Volts and the photovoltaic panel current is about 5.45 Amps is shown in Figure. 9. Figures 10 & 11 show that the output voltage is about 23 volts and output voltage T.H.D is about 10.43 % of ANPCMLI respectively.

Table 3 shows the comparison of various modulation strategies for ANPCMLI. By employing PDPWM technique, it was found that the harmonics are reduced in the output voltage compared to other PWM techniques for the proposed MLI.

Hardware Implementation For Three Phase 3-Level Active Neutral Point Clamped Multilevel Inverter:

The hardware prototype of the proposed three phase ANPCMLI is developed using IGBTs as power device, along with isolation and driver circuit etc. The gating pulses were obtained from a Xilinx-FPGA SPARTAN 3E board. The hardware set-up for three phase ANPCMLI is shown in Figure. 12.


FPGA Implementation:

The hardware prototype presents the development of Xilinx-FPGA SPARTAN 3E as a control circuit for three-phase active neutral point clamped multilevel inverter. Eighteen I/O lines of SPARTAN 3E are used as PWM output lines for three phase 3-level active neutral point clamped multilevel inverter output voltage. VHDL language is used to model the multicarrier PDPWM switching strategies and Xilinx ISE 14.1 software is used as a simulation and compiler tool. The VHDL code successfully embedded in FPGA is shown in Figure. 13.The gating patterns of the switches of single phase active neutral point clamped multilevel inverter obtained experimentally are shown in the Figures. 14-19.








Figures 20-22 show that the input voltage of three phase ANPCMLI from photovoltaic panel, output phase voltage and line to line voltage of ANPCMLI respectively.





This paper has successfully presented the implementation of ANPCMLI powered by PV source. By suitably developing the PDPWM technique in FPGA, appropriate phase and line to line voltage output was obtained for the three-phase active neutral point clamped multilevel inverter. By using PDPWM it is found that the spectral quality of the output voltage of the proposed MLI is improved. The simulation results are verified experimentally. Therefore, the proposed ANPCMLI is a suitable choice for photovoltaic applications.


Article history:

Received 3 September 2014

Received in revised form 30 October 2014

Accepted 4 November 2014


The authors wish to thank the management of SSN College of Engineering for providing the financial support to carry out this research work.


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(1) A. Bharathi sankar and (2) Dr. R. Seyezhai

(1) Full time research scholar, Department of Electrical and Electronics Engineering, Kalavakkam, Chennai. Tamilnadu, India.

(2) Associate professor, Department of Electrical and Electronics Engineering, Kalavakkam, Chennai. Tamilnadu, India.

Corresponding Author: A. Bharathi sankar, Full time research scholar, Department of Electrical and Electronics Engineering, Kalavakkam, Chennai. Tamilnadu, India.
Table 1: Conduction table for ANPCMLI

Voltage level   T1   T2   T3   T4   T5   T6

Vdc             1    1    0    0    0    1
V dc/2          0    0    1    1    1    0
Zero            1    0    1    0    0    1

Table 2: Simulation parameter for ANPCMLI & PV panel

Simulation parameter   Values

Photovoltaic panel     [V.sub.[varies]] = 21.5 V
                       [] = 5.5 A
                       P = 100 W
                       N = 36 cells
Active neutral point   [] = 22V
clamped multilevel     [f.sub.s] = 3KHz
inverter               [m.sub.a] = 1
                       [m.sub.f] = 60

Table 3: Comparison of various modulation strategies for ANPCMLI

MI    PD        POD       APOD      PS
      PWM       PWM       PWM       PWM

0.5   12.37 %   14.94 %   14.88 %   18.83 %
0.6   12.12 %   14.63 %   14.46 %   18.72 %
0.7   11.93 %   13.97 %   13.83 %   17.99 %
0.8   11.15 %   13.52 %   13.45 %   17.45 %
0.9   10.52 %   12.72 %   12.63 %   17.23 %
1.0   10.43 %   12.82 %   12.74 %   16.62 %
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Article Details
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Author:Sankar, A. Bharathi; Seyezhai, R.
Publication:Advances in Natural and Applied Sciences
Article Type:Report
Geographic Code:9INDI
Date:Dec 1, 2014
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