Signal integrity applications of Mathcad, part 3: Mathcad allows Fourier transformation, convolution, SI modeling and simulation of PCB topologies.
[FIGURE 9 OMITTED]
As an example, FIGURE 9 presents a complex time domain vector [g.sub.n] with real part [Re ([g.sub.n])] and imaginary [Im ([g.sub.n])]. There are M data points at sample spacing P (with reciprocal fp). n represents an index/integer and [omega]0 is angular frequency, [t.sub.n] and [frq.sub.n] are horizontal axes for time and frequency plots respectively. Mathcad CFFT is executed to generate the vector [G.sub.n] in frequency space.
Furthermore, ICFFT can be operated on [G.sub.n] to reproduce [g.sub.n].
This implies the Fourier transform pair: G := CFFT(g) and g := ICFFT(G).
Fourier transform possesses remarkable applications in high-speed digital design. Digital signals can be approximated by square waves, (18) having wide bandwidths or many frequency components. Fourier expansion can evaluate the spectral content (or harmonics) of such periodic time domain waveforms.
TDR measurements are related (19) to corresponding VNA measurements via Fourier transform.
Another notable feature of Fourier transform is that convolution in time domain, often difficult to compute, is converted into a simple multiplication (20) in frequency domain.
A discrete-time approximation to the Fourier transform called DFT forms a foundation for fundamental techniques and applications of digital signal processing (DSP).
Johnson, et al (4) have simulated pulse propagation by applying Mathcad's FFT/IFFT feature. Norte (3) has also illustrated Mathcad's simulation of single-ended and differential high-speed topologies.
Consider the single-ended topology in FIGURE 10, which includes a driver U1, a transmission line T1 and a receiver U2. T1 has bandwidth (Bw) and characteristic impedance (Zo). U2 can be modeled by parasitic resistance (Rr) in series with capacitance (Cr).
U1 outputs a series of pulses having bit period (Tb) and launches a voltage waveform (Vp) at input of T1. These signaling schemes can be simulated using various tools, including SPICE or SI tools from companies such as Mentor Graphics, Cadence, Ansoft and others. It can be also solved by Mathcad, which provides an economical (21) approach for generating dependable results and design guidance. (21)
[FIGURE 10 OMITTED]
Application of Mathcad for simulating such single-ended signaling is demonstrated by FIGURES 11 and 12.
In FIGURE 11, Bw symbolizes the transmission line bandwidth in Hz. Zo equals line impedance (ohms). Tb represents the input pulse's bit period in seconds. Rr is the load series resistance and Cr the load capacitance (Farad). Rr is usually on the order of milli-Ohms, and Cr includes C_comp and C_pkg. (22)
FIGURE 11 involves transmission of a series of bits across the interconnect. The data pattern is encoded with industry-standard non-return-to-zero (NRZ) format. In NRZ, the binary 1 and 0 are a positive and a negative square wave pulse respectively.
The uni(t) function aids in forming the NRZ bit waveform. The load impulse response ignoring propagation delay is impr(t). The vstp(t) models the transmission line as a first-order low-pass filter. The pulse waveform just before the receiver equals vstp(t)--vstp(t-Tb). The convolution integral of this waveform and impr(t) yields the output voltage Voutp(t), which is sectioned into Vout1(t) and Vout2(t). The difference Voutp(t)--Voutp(t-Tb), in turn, produces the received pulse Vrec(t). Finally, vnrz(t) is the NRZ 50-bit stream, which is expressed as summation s1(t) + s2(t)+ ... +s10(t).
vnrz(t) as depicted by FIGURE 12A consists of:
An eye pattern at the receiver can be constructed via bit-by-bit superposition of the received bits.
FIGURE 12B shows an eye pattern formed by graphing 16 bits on the same graph. The plotted bits embrace vnrz(t+Tb), vnrz(t+2Tb), .......... vnrz(t+15Tb), vnrz(t+16Tb). Plotting several Y-axis expressions versus the same X-axis in Mathcad requires entering the first expression followed by a comma. A placeholder will then appear below the first expression. When the second expression is entered followed by a comma, another placeholder results for entering the next expression. This process can be repeated to graph multiple expressions.
Eye diagrams are frequently generated employing a large number of pseudorandom bit sequence (PRBS), such (23) as a PRBS [(2^7) - 1]. However, eye patterns created by Mathcad based on a limited number such as 16 bits can be still valuable particularly for examining trends. (21) For instance, it can be useful for analyzing effects on the eye pattern caused by variations in bandwidth or load capacitance. Trends based on 16 bits can be quite similar to those associated with a much greater number of signal bits.
As an example, decreasing the line bandwidth (Bw) (in FIGURE 11) from 500 MHz to 100 MHz will reveal degradation in eye opening of FIGURE 12B.
Consider a differential topology as displayed by FIGURE 13. It comprises a differential driver (U1), transmission lines (T1, T2, T3 and T4), termination resistor (Rt) and differential receiver U2. The concepts governing single-ended signaling can be extended to differential case, but it requires several important considerations.
Differential signaling involves propagation of signals on a pair of coupled transmission lines. The degree of coupling influences impedance, signal velocity (timing) and termination requirements.
The non-inverted signal Vp traveling on one line is the complement of an inverted signal Vn on the second line. For instance, if Vp is given by:
Then Vn having opposite polarity (each "1" is replaced with a "0" and vice versa) consists of:
The differential receiver acquires the difference Vp--Vn to ascertain the high or low state of the received signal. The reason for capturing the voltage difference is to minimize the common-mode noise. Mathcad scripts for treating differential topologies are described in Reference 3, found in Part I of this series.
In conclusion, Mathcad can be effectively applied for analyzing signal-integrity concepts, solving complex signal-integrity expressions and simulating high-speed PCB topologies.
[FIGURE 11 OMITTED]
[FIGURE 12 OMITTED]
[FIGURE 13 OMITTED]
(18.) Stephen H. Hall, Garrett W. Hall and James A. McCall. "High-Speed Digital System Design, A Handbook of interconnect Theory and Design Practices, John Wiley and Sons Inc., 2000, p. 85.
(19.) "TDR and VNA Measurement Primer" Application Note, 2004, TDA Systems Inc.
(20.) Zack Settel and Cort Lippe. "Real-Time Frequency-Domain Digital Signal Processing on the Desktop;' Proceedings of the 1998 International Computer Music Conference. San Francisco Music Association, pp. 142-149.
(21.) David Norte "Transmission Line Discontinuity With a Series RC Load" www.the-signal-and-power-integrity-institute.com.
(22.) Abe Riazi. "Stub or no Stub?" Printed Circuit Design and Manufacture, October 2004, p. 18.
(23.) Chih-Kong Ken Yang, Ramin Farjad-Rad and Mark A. Horowitz. "A 0.5-um CMOS 4.0-Gbits/s Serial Link Transceiver with Data Recovery Using Oversampling" IEEE Journal of Solid-State Circuits, vol. 33, no. 5, May 1998, pp. 713-722.
DR. ABE (ABBAS) RIAZI is a senior staff electronic design scientist with Broadcom Corp. in Irvine, CA, and can be reached at ariazi@ broadcom.com.
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|Title Annotation:||INTERCONNECT STRATEGIES|
|Author:||Riazi, Abe "Abbas"|
|Publication:||Printed Circuit Design & Fab|
|Date:||Aug 1, 2008|
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