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Shoot through time-based controlled pulse generation for Z-source inverter.

1. Introduction

Due to insufficient energy supply for large appliances, there is a need to incorporate novel inverters with the suitable controlling pulses to provide high output for different applications such as Flexible AC transmission systems (FACTS) (Sotoodeh and Miller 2014), photovoltaic generators (Liu et al.2016), electric motors (Guo et al. 2013) and uninterruptable power supplies (UPS) (Zhang et al. 2016. The static power inverter functions to produce fast transition by the action of fully controllable semiconductor power switches. Here, the different modulation techniques such as pulse-width modulation, space vector technique and carrier-based technique play an important role in controlling the switching frequency. The different types of the inverter are voltage source inverter, current source inverter, and multilevel inverter that are used for designing the controller. The difference between these types of inverter is DC links and number of diode requirement. The multiple voltage level inverter topologies are involved in a multilevel inverter for high voltage and power operations with low distortion. But, the high-power semiconductor device is necessary to apply in this multilevel inverter at a distributed high-voltage level. Practically, the current source inverter is an application for three-phase application where high-quality voltage waveform is required. The switching losses are doubled in current source converter by increasing the reverse voltage withstanding capability. The DC-link voltage from current source converter is lower than the peak voltage level for AC signal. Thus, the voltage source inverter is utilised as either buck or boost inverter to avoid the over-modulation operation which is present in the current source inverter. The two source inverter comes across one of the types of Z-source inverter (Siwakoti et al. 2015) of three-phase inverter which functions as a buck-boost inverter to alter the DC to AC without utilisation of DC-DC converter separately. The inverter topology is classified into two types such as three-phase inverter with high voltage battery and three-phase Pulse Width Modulation (PWM) (Bhutia, Ali, and Tiadi 2014). Due to a reduction in harmonic content, the switching frequency is designed with a high range which causes increase in switching loss. To solve this switching loss issue, the pulse-width modulation method is developed and it is classified into different categories (Zhang, Thomsen, and Andersen 2013; Lei and Peng 2014). The harmonic power loss and voltage/current ripples are the parameters affected by having different switching sequence arrangements. The DPWM technique is utilised to reduce the switching frequency by selecting only one zero vector in one sector. Further, the DPWM method is required to maintain total harmonic distortion (THD) and reduction in switching loss. Thus, the PWM has some due to available constraints of AC output voltage below the DC input voltage. Hence, the DC-DC boost converter is needed between the DC source and inverter to offer the desired AC voltage. This additional requirement of converter increases the cost and lowers the efficiency. To prevent the short through at each phase leg which causes the waveform distortion of the AC output voltage, both upper and lower devices of each phase leg are blocked to provide the dead time in the inverter.

The Z-source inverter (ZSI) (Zhou, Li, and Li 2016) is developed in order to overcome the waveform distortion limitation in the inverter. The special features that involved in the design ZSI are represented as follows:

* It performs the DC-AC power conversion for obtaining the desired AC voltage that is greater than the sour line voltage.

* It does not require any dead time, because the short circuit is allowed across any phase leg.

* Also, it suppresses the voltage effectively by the use of second order filtering technique rather than using the capacitor in the traditional PWM inverter.

* Moreover, the in-rush current and harmonics in the current are reduced due to the action of an inductor.

But, the traditional inverter design does not have these features, thus this work develops the ZSI with these features. Here, the harmonics are reduced by using different control modulation technique in the Z-source inverter. During maintenance of a constant boost, the control method announces the low output frequency to attain maximum voltage boost/gain. The optimisation is required with merits of simplicity, less complexity in PWM control technique. The role of optimisation technique is tuning control method optimally to minimise the THD output voltage (Sargolzaei et al. 2015). The major contributions of this work are as follows:

To invert the input DC voltage with minimum short through time, the feedback topology is enhanced with the provision of controller design.

To provide the regulated output voltage, the space vector pulse width modulation technique is implemented. To eliminate the harmonic distortion in the output voltage, the dragon fly optimisation and dq0 transformation techniques are implemented.

The paper is organised as follows: The detailed description about the related works on three phase inverter with the controlling topologies is presented in section II. The implementation process of proposed short through time-based controlled pulse generation (SST-CP) is described in section III. The performance of proposed SST-CP is investigated with the various performance parameters in section IV. Finally, the conclusions about the application of proposed work on voltage regulation are presented in section V.

2. Related works

This section discusses the issues in the traditional controlling topologies to generate the regulated output voltage. The impact of the controlling pulses from the modulation technique for harmonic minimisation is also described in detail. The minimisation of stress on the switching devices, isolation, and high-efficient output voltage are the major factors in the design of Z-source inverter. Liu (2014) investigated space vector modulations (SVM) for the three-phase Z-source/quasi-Z source inverter in terms of different parameter calculation such as shoot-through duty ratio, switching control pattern and voltage stress across the switch. The total average switch device power and shoot-through current stress were determined by computing the total stress of the power. The modulation with different pulse width modulation and control techniques were required to match the various application requirement and utilisation of impedance-source network properties. The second harmonic voltage and current ripples exist in the quasi Z-source inverter. Ge (2016) integrated active filter into the quasi-Z-source inverter (qZSI) to ensure both constant inductor currents and voltages by transferring low-frequency power ripples directly from AC load to active filter's AC capacitor which represent that the low-frequency power ripple does not present in DC side. Finally, the high-frequency ripple was smoothened by employing small qZS impedance and AC voltage supported by active filter capacitor in the system. But, this active power filter method increased complexity and number of components in this integrated circuit. Babaei (2016) developed switched Z-source inverter topology to reduce the weight, cost, and size of the number of active elements. Based on a switched-inductor cell, the developed topology solved the issue of a short circuit across the inverter leg. Also, the number of passive elements was reduced by completely analysing the topology with different operating modes in terms of voltage gain, ripple in both capacitor and inductor voltage and current. Even though this switched ZSI topology has high voltage gain, this topology has the limitation of high voltage stress on the capacitor. Li (2016) suggested commutation torque ripple reduction strategy on the basis of Z-source inverter for brushless DC motor (BLDCM). The similar two-phase modulation mode was engaged in both the normal conduction and the commutation period. Then, the shoot-through vector and active vector duty cycles were regulated to reduce the commutation torque ripple. The end point of commutation was acquired by comparing the clamped terminal voltages with reference zero level and the attenuation of the terminal voltages was avoided to improve the signal-noise-ratio. Thus, the commutation torque ripple and detection of an end point of commutation were achieved by utilising the pulse width of the shoot-through vector. Further, this system was required to minimise torque ripple during indication of converter response. Vadizadeh (2013) announced involvement of two methods such as line voltage and Fourier coefficients in the three-phase inverter to estimate all possible THD. These distortion values were minimised by identifying the switching angles for all harmonic orders of the two-level inverter and deriving analytical formulas for the line voltage THD. Liu (2016) integrated active power filter (APF) and single-phase quasi-Z-source Inverter (qZSI) to avoid second harmonic power from the DC side with the help of half-bridge leg and AC capacitor. The capacitance of both DC and AC side was reduced by buffering the second harmonic power of the load and allowing highly pulsating AC voltage, respectively. The second harmonic power of single-phase qZSI was tracked by predicting the capacitor voltage of APF with the help of direct power control (DPC) in the integrated topology to avoid this distortion. He (2016) cascaded two Z-source neutral points clamped inverter in series to improve the running efficiency and reduce the harmonic content. This cascaded Z-source inverter was controlled by applying the alternative phase opposition disposition (APOD) carrier-based modulator. The boost factor of this inverter was increased from 1/(1 - 2D) to 1/(1 - 4D). This Z-source NPC topology concentrated on two parameters such as capacitor voltage and inductor current stresses. Sajadian and Ahmadi (2016) integrated two components of model predictive-based maximum power point tracking (MPPT) and the gridside power injection controller in the control strategy1e for ZSI-based grid-tied PV system. This model shifted the PV voltage to the voltage at MPP and this shifting was processed by the predictive-based MPPT algorithm to track the maximum power point (MPP) in the PV module. Bakeer (2016) developed finite control set-model predictive control (FCS-MPC) algorithm to control the number of calculation for different sampling time. Through the decision of required state, the setting point of inverter capacitor voltage, inductor current, and output load currents was controlled in developed strategy to reduce computational power by selecting either shoot through (ST) case or the other non-ST case. The low-cost processors were obtained by saving the number of calculations in terms of choosing ST case without passing through the loop and including a single weighting factor for the capacitor voltage. Even though this system removed the output error as fast, it was possible to provide stability problem and insufficient achievement of system performance. Kayiranga (2016) suppressed frequency resonance by utilising the asymmetric impedance network-based quasi-Z-source PV inverter (AIN-qZSI) after a complete analysis of the effect of occurrence of abnormal states in order to reduce the impedance network. Based on the state transition diagram, a control strategy was developed for suppressing the frequency resonance to reduce the impedance network losses. Qi (2014) suggested active power decoupling topology for PWM rectifier to attain both sinusoidal input current on the AC side and ripple power decoupling on the DC side without additional switches. This decoupling topology in PWM utilised an auxiliary decoupling capacitor to reduce the usage capacitance in the converter and second-order ripple voltage on the DC-link. But withstand voltage of the auxiliary capacitor was lesser than the DC-link capacitor. Due to the insufficient usage of fully controlled switches, this rectifier limited the input power and flux variation in some output current ripple. The simpler controller design was required to complement converter operation. Due to the availability of bulk capacitor bank for ripple power filtering, the rectifiers resulted in lower power density. Thus, Li (2013) enhanced active power decoupling with a third leg, energy-store capacitor, and a smoothing inductor to improve the high-energy storage and reduce the control bandwidth requirement. Also, this single-phase PWM rectifier had the ability to achieve high power applications by fully utilising the capacitor's energy storage and without excessive current stresses in the power devices. But, the residual ripple power was still available during the action of dual-loop capacitor voltage control system due to the modelling of steady-state error. In the decoupling circuit, the voltage stress was obtainable as high for both action of switches and capacitor. Even though effective ripple power consumption was obtained, this topology was inapplicable to unfolding bridge-based inverters. Wang (2011) minimised energy storage capacitance by considering a bidirectional buck-boost converter as the ripple energy storage circuit for single-phase rectifiers. The feasibility of the active capacitor's reduction strategy was verified on the basis of minimum ripple energy requirement which was derived independently with a specific topology. The single-phase on-board PEV charging systems were required to analyse the suitable topology for V2G reactive power operation. Cha (2016) investigated high-frequency loops in the various Z-source inverters to avoid generating severe voltage overshoot in the dc-rail voltage of the ZSIs. By utilising an intuitive circuit modification along with clamping diode in the dc-rail voltage clamping technique, the magnetically coupled impedance source converters was processed to solve voltage overshoot problem across the dc-rail of the ZSI. This MCIS converter affected the other waveforms which were required to process the converter without affecting other waveforms. Zhou (2016) reduced the capacitance requirement by utilising the control strategy to buffer the double-frequency ripple (DFR) energy in single-phase Z-source/quasi-Z-source inverter applications without utilising excessive hardware components. But this control strategy led increased switching device voltage stress and power loss. The smaller size ceramic capacitor with large voltage swing was required to store the pulsation energy in an auxiliary buffering capacitor which was attached to the DC bus. Also, this system was required to change the bulky capacitor as small capacitors in an electronic circuit. Farokhnia (2013) solved line-to-line voltage problem of THD for three-level inverters by introducing two methods such as integrating method and formula method. All harmonics were obtained by using these two methods. The integrating method was used for any number of controlled pulse width modulation (PWM) switching angles. The distinct superior was attained by utilising the formula method for both simplicity and calculation of run time viewpoint, but it was limited to a low number of controlled PWM switching angles. This method was unable to extract the optimum switching angles for minimising the THD. Due to incomplete parameter definitions, the inverter was required to utilise elegant theory in all domains. Also, this system had some drawbacks such as divergence problem, the requirement of a precise initial guess, no optimum solution. The increase of switching frequency takes very low settling time for the DC output. The generation of static control signals resulted leads to high harmonic distortion. This paper proposes the new control methodology based to alleviate the issues observed in the existing models.

3. Proposed shoot through time-based controlled pulse generation

This section discusses the implementation of proposed space vector pulse width modulation (SVPWM) with a new controlling technique for regulating AC output from Z-source inverter. Figure 1 shows the workflow of the proposed STT-CP with new modelling of SVPWM in inverter for the regulated output voltage.

The components such as Z-source inverter, SVPWM, IGBT switches, and filter are used in the circuit design. Initially, the DC signal is passed to the Z-source inverter as the input signal. The role of Z-source inverter is a conversion of DC signal to AC signal without a requirement of the additional DC-DC converter. Here, the Insulated Gate Bipolar Transistor (IGBT) reacts as a switch to perform the conversion process. The total number of the voltage-controlled device of IGBT switches utilised in the inverter process is six which are actively participated to produce the results. The conversion process is operated based on the different controlling technique. Here, the Space vector pulse width modulation technique (SVPWM) is modelled with the computation of three parameters such as switching frequency, duty ratio, deviation of phase angles in voltage and current. In our research work, the DC input voltage is represented as constant amplitude vector rotating at a constant frequency which is processed with the space vector pulse width modulation technique to obtain three phase sinusoidal voltage. This control method approximates the reference voltage by the combination of six switching pattern of the inverter. The space vector PWM technique is the best technique among the other techniques for controlling the inverter in variable frequency AC drive applications. These new controlling technique coupled with space vector PWM for providing the better result by using the shoot through time period which is obtained by using the equation 12. This technique also reduces the occurrence of ripples with the switching frequency. The pulses required to trigger the IGBT switches in the ZSI inverter are generated through SVPWM block. Based on this SVPWM controlling technique, the IGBT switches on/off to perform conversion from DC to AC. The noise in the resulted space vector pulse modulated with IGBT switches are removed by using the second-order lowpass filter. Finally, the THD is reduced by using the proposed topology to obtain regulated AC output of constant DC input signal.

3.1. Circuit description

The construction of the high-efficient Z-source inverter with the SVPWM-IGBT is the major objective of this paper to meet the desired needs of AC output with regulation from DC input with reduced harmonic distortion. The application of proposed SVPWM modelling depends on the minimum switching losses, minimum ripple occurrence during the energy transfer between the actions of IGBT switches. These switches have the higher potential to provide the lossless switching for the regulated output AC. The basic circuit diagram for the proposed work is illustrated in Figure 2.

The circuit diagram consists of several inductors, capacitor, transistor and a resistive load to perform the alternating current conversion. The two inductors named as [L.sub.1] and [L.sub.2], two capacitors named as [C.sub.1] and [C.sub.2] are utilised as Z-source network by connecting it in X-shape inverter. These elements of the inverter are coupled with DC voltage source which may be a battery, diode rectifiers or fuel cell. The voltage source is widely varied with a current drawn from the source storage. Due to the possible of inability production of AC voltage from the inverter, the boost DC-DC converter is required and it is greater than the DC voltage. But, the desired AC voltage is obtained without considering the DC voltage source by using the Z-source inverter. The six active voltage vectors and one zero voltage vector are utilised in the general type of ZSI inverter. In three-phase ZSI, one extra zero voltage vector is accessible when the load terminals are shorted through both the upper and lower switching devices of any phase leg. From the two operating modes of ZSI such as non-shooting through mode and shoot-through mode, the proposed topology utilises the shoot-through mode for providing the better result.

The load terminals shorted both the upper and lower switching devices of any phase leg are represented in Figure 3 which indicates short-through mode. The derivation for capacitor voltage is followed by assuming the inductors ([L.sub.1] and [L.sub.2]) and capacitors ([C.sub.1] and [C.sub.2]) which are contained some inductance and capacitance value, respectively.

Let us consider the inductor and capacitor voltage from the equivalent circuit as

[mathematical expression not reproducible] (1)

The input voltage of the inverter becomes zero in Figure 3 when the ZSI is in the shoot through the state for a period []. The expression for inductor voltage is derived as

[V.sub.L] = [V.sub.C] (2)

The capacitor voltage is derived by considering the average of an inductor voltage over one switching period [T.sub.s] as zero value and its equation is followed below.

[mathematical expression not reproducible] (3)

where, the switching period is derived from the formula of [T.sub.s] = [T.sub.n] + [] and [T.sub.pu] = []/[T.sub.s] expression denotes the shoot-through time for specific duty ratio.

The shoot-through time is based on the capacitor voltage which in increased by improving the shootthrough time. Due to having zero value for an average of an inductor voltage, the capacitor voltage is identical to the average of the DC link voltage across the inverter bridge. The shoot-through time duty ratio and DC input voltage are utilised to calculate the peak of the DC-link voltage which is equivalent to the DC input voltage.

[mathematical expression not reproducible] (4)

3.2. Proposed controller design

The DC boost control and the AC output voltage control are included in the ZSI which is shown in Figure 4. Through the feedback signal, the DC input voltage is processed by using the SVPWM based three phase inverter for conversion of DC into AC. There are three inputs provided to the SVPWM. Initially, the gain value is obtained by comparing the input DC voltage and output voltage after performing the optimisation technique. Based on these gain value, the shoot-through time is calculated with the help of integrator computation. In a similar way, the reference voltage is provided to the space vector modulation after integrating the gain value of optimised output voltage and input DC voltage. Finally, the phase angle of the input voltage is provided to the SVPWM. Thus, these three inputs are processed in the proposed ISVPWM and its operating mode is described in the below section. At the final stage, the three-phase AC voltage is obtained by controlling the DC source voltage with the help of the space vector modulation technique. The novelty of the proposed technique is, it generate the pulses for the inverter by implementing the dragon fly optimisation and Abc to dq0 transformation techniques. In this transformation, the time varying inductances are removed by changing the stator and rotor quantities into the fixed/rotating reference frames. Moreover, the feedback topology is improved for inverting the input DC voltage with the minimum short through time. Also, the proposed SVPWM provides the regulated output voltage with reduced harmonic distortion.

Here, the dq0 transformation is utilised which is also called as park transform and it is the process of changing the stationary phase coordinate system (ABC) to a rotating coordinate system (dq0). This process of changing stationary frame represents the space vector transformation of three-phase time-domain signals. The aim of the proposed system to use the optimisation technique is to provide the best position and dragonfly algorithm is utilised as the optimisation technique. By doing this process, the new controlling space vector technique reduces the THD by reducing the time-varying inductance of the switching voltage. This process produces different shoot through time, reference voltage, and phase angle to accurately invert the input DC voltage into AC voltage.

Due to shoot-through state of ZSI, the DC link voltage is increased by using both upper and lower switches of any phase leg. After that, the desired AC output voltage is greater than the available DC link voltage by boosting the voltage with the help of proposed ZSI. The shoot-through time duty ratio is controlled to boost the capacitor voltage Vc which is equivalent to the DC link voltage of the inverter. The shoot through time period is impossible to linearly control the capacitor voltage. Thus, the transient response of capacitor voltage is affected by this nonlinearity action. The proposed voltage control design of ZSI is utilised for controlling linearly the capacitor voltage to overcome the nonlinearity issue. The output of the PI controller of capacitor voltage ([V.sub.C]) becomes [K.sub.C] and it is defined as the

[mathematical expression not reproducible] (5)

where [K.sub.C] is greater than 1 for increasing the capacitor voltage. The proposed controller design in terms of formula calculation is described below.

[mathematical expression not reproducible] (6)

where t is represented as the time at each iteration, [T.sub.s] is indicated as sample time interval, [V.sub.dc] is denoted as DC voltage, and [K.sub.c] represents the controller gain.

The dq0 transformation is performed to calculate the switching voltage and shoot-through time period. Here, the input voltage is converted into stationary frame.

[mathematical expression not reproducible] (7)

[mathematical expression not reproducible] (8)

[mathematical expression not reproducible] (9)

where, [empty set] represents 180[degrees], phase angle is represented as [omega], time period is denoted as t, [v.sub.a], [v.sub.b] and [v.sub.c] indicates output voltages. From the Equations (8)-(10), the switching frequency and shoot-through time calculation is described below.

[mathematical expression not reproducible] (10)

[mathematical expression not reproducible] (11)

where [V.sub.s] indicates the switching voltage, [] denotes shoot through time, the duty ratio is represented as k, and switching period is indicated as [T.sub.s]. With these deciding factors from (11) to (12), the pulses necessary to trigger the switches are generated to regulate the output voltage across the load.

3.3. Improved space vector PWM (ISVPWM)

Due to having the lower current harmonics and a higher modulation index in Space vector PWM (SVPWM), it is widely used in industrial applications of the PWM inverter. The shoot-through time in ZSI is controlled by using the space vector pulses with the help of SVPWM which utilises the eight space vectors [V.sub.0]-[V.sub.7] where [V.sub.1]-[V.sub.6] are active vectors and two vectors are zero vectors such as [V.sub.0], [V.sub.7]. If the reference voltage vector [V.sub.ref] is situated between the arbitrary vector [V.sub.i] and [V.sub.i + 1], the reference voltage vector is partitioned into the two adjacent voltage vectors ([V.sub.i] and [V.sub.i + 1]) and zero vectors ([V.sub.0], [V.sub.7]). The zero vector is applied in one sampling interval at time [T.sub.0] = [T.sub.s] - ([T.sub.1] + [T.sub.2]). Simultaneously, the two adjacent voltage vectors are applied at time [T.sub.1] and [T.sub.2] with respect to the [V.sub.i] and [V.sub.i + 1]. Thus, the reference voltage vector [V.sub.ref] is derived as the flowing equation.

[mathematical expression not reproducible] (12)

The switching patterns for improved SVPWM (ISVPMW) are shown in Figure 5 when the reference voltage vector is at sector I. The switching pattern is analysed on the basis of four operating modes with the consideration of different directions of the current flows and the switching voltages. The dead time is calculated based on the difference between the time taken to rise up for two switching operations and it is provided to prevent the short circuit between each phase leg by hindering both the upper and lower switching devices at each phase leg. During the conduction period of switches, the output voltage is boosted and reduced to ensure the minimum setting level. The controlling pulses from the ZSI based SVPWM reduce the harmonic distortion that improves the efficiency effectively.

The operating mode of six IGBT switch in the proposed circuit is divided into four steps which are discussed with current flow directions and the operation of the device.

3.3.1. Mode 1: (0-[T.sub.1])

In this mode 1, the switches [Q.sub.1],[Q.sub.4],[Q.sub.5] are ON and the other switches such as [Q.sub.2],[Q.sub.3],[Q.sub.6] are OFF. The corresponding current ([I.sub.dc]) flows in the circuit between input source to the resistive load through the inductor, capacitor, and diode combination. Due to the short circuit of [Q.sub.1],[Q.sub.4],[Q.sub.5], the capacitor ([C.sub.2]) and inductor ([L.sub.2]) gets charged. The charging operation ends at [T.sub.1]. The output voltage is raised to the amplitude ([V.sub.DC] + [V.sub.c]) accordingly due to the capacitor charging.

3.3.2. Mode 2: ([T.sub.1]-[T.sub.2])

In this mode 2, the switches [Q.sub.1],[Q.sub.4],[Q.sub.6] are ON and the switches [Q.sub.2],[Q.sub.3],[Q.sub.5] are OFF. The current (Idc) flows through the combination of inductor, capacitor and diode. In this stage, the capacitors ([C.sub.1], [C.sub.2]) starts discharging its energy to the load. Hence, the additional current flows through the inner loop. The combination of discharging and the additional current flow maintains the output voltage at ([V.sub.DC] + [V.sub.c]) level till [t.sub.2].

3.3.3. Mode 3: ([T.sub.2]-[T.sub.3])

In this mode 3, the switches [Q.sub.2],[Q.sub.3],[Q.sub.6] are ON and the switches [Q.sub.1],[Q.sub.4],[Q.sub.5] are OFF. In this stage, the capacitors and inductor ([L.sub.1], [C.sub.1]) gets charging again till [T.sub.3] due to the short circuit of [Q.sub.2],[Q.sub.3],[Q.sub.6]. Hence, the current passes through the inner loops in order to attain the resistive load. The combination of charges and the inductor current flows maintains the output voltage at ([V.sub.DC] + [V.sub.c]) level effectively.

3.3.4. Mode 4: ([T.sub.3]-[T.sub.4])

During the time period ([T.sub.3]-[T.sub.4]), the switches [Q.sub.2],[Q.sub.3],[Q.sub.5] are ON and the switches [Q.sub.1],[Q.sub.4],[Q.sub.6] are OFF. The voltage across the capacitor [C.sub.1] starts discharging through [Q.sub.1] loop and the voltage at the capacitor [C.sub.2] discharged to the load. The capacitor current flows through the inner loop and the load.

By performing this mode of operation, the output waveform is obtained to find the shoot through states which are assigned evenly to each phase within zero voltage time period. Without changing the active states, the shoot-through time is generated by reducing the zero voltage period. Thus, the PWM control of the inverter is not affected by the presence of shoot-through time.

The input DC voltage is processed with space vector pulse width modulation to control the shoot-through time in ZSI with lower harmonics and higher modulation index. This switching voltage and shoot-through time are utilised to reduce the THD. To obtain the regulated AC output, the distortion reduced output voltage is processed with second-order low pass filter, where the frequency response properties are obtained by using the RC networks.

4. Experimental results

The configuration of proposed circuit is illustrated in Table 1. With this configuration, the proposed circuit is simulated by using the MATLAB Simulink tool.

The FFT analysis of the output voltage from the existing and proposed converters are shown in Figure 6(a) and (b). With the variations of frequencies, the magnitude of fundamental and harmonic components is measured. The provision of ZSI-based ISVPWM regulates the DC output voltage and reduces the harmonic level. The THD value of the FFT analysis is 1.17% for the input DC voltage of 100 V. The controlling of current variations by the additional inductor and capacitor in the proposed circuit reduces the turn-off a spike in switches that lead to minimum harmonics observed with respect to the output voltage. The closed loop control through the ISVPWM topology proposed in this paper has significant contributions in the design of the reliable ZSI.

From Figure 6, it is analysed that the existing system has 2.57% THD with 10000 samples per cycle, 10.73 DC components, and 180.3 fundamental components, which consumes the power factor as 0.9909. But in the proposed system, it has 1.16% of THD with respect to 10000 samples per cycle, 1.148 DC components, and 432.1 fundamental components, which consumes the power factor as one. In this evaluation, it is proved that the proposed SVPWM efficiently reduced the harmonics, when compared to the existing controller design. Figure 7 shows the resultant capacitor voltage for the proposed space vector-based ZSI inverter. From the figure, the capacitor voltage ([V.sub.C]) is linearly increased for some time by utilising the new controlling technique on vector modulation. The charging and discharging of capacitor value by controller action on switches changes the capacitor voltage. After that, the capacitor voltage is slowly decreased for specific time period. Here, the capacitor voltage is evaluated by comparing the resulted output of voltage (y-axis) with respect to the time period (x-axis). At the final stage, [V.sub.C] is maintained at a constant level without any variation.

Figure 8 shows the experimental results of the duty ratio of ZSI. Due to the direct proportion of duty ratio and the capacitor voltage, the decay ratio (k) is linearly increasing in the starting time period. After some time, it is slowly reduced for particular time period. For the time period 0.02, the duty ratio is increased from above 90 to above 100. Due to the capacitor charging and discharging operation, the duty ratio is increased for a specific time period. Then, k is decreased slowly upto 0.07 time period and maintain constant value from 0.07 to 0.1 time period.

Figure 9 shows the waveform of the three-phase output voltage at steady-state operation when the provided DC input is 100 V. From the figure, it is analysed that given constant amplitude voltage is changed into three-phase AC output voltage which is represented by a sinusoidal waveform. The phase amplitude of the output voltages is maintained constant for each phase by optimum discharging of capacitor value and switching level (on/off).

5. Conclusion

This research work developed a new controlling technique, namely, SVPWM that is integrated with the Z-source inverter for reducing the THDs and ripples in an efficient manner. In this design, the IGBT switches are used to perform the inverter operation based on the space vector pulses generated by the controller, which linearly controls the capacitor voltage. The AC output voltage is obtained with respect to the peak voltage by increasing the transient response of the DC input voltage. Here, the three phase voltages generated from the controlled AC pulses are processed by the use of direct quadrature zero transformation, which transforms the voltages into the stationary frames. Moreover, the dragon fly optimisation algorithm is used to calculate shoot through and switch voltage by estimating the best position. The parameters such as shoot through time, switching voltage, and phase angle are calculated for efficiently reducing the total harmonics. So, the proposed three phase inverter circuit provides the better fundamental component for the input voltage. In experiments, the performance of the proposed SVPWM and ZSI circuits are evaluated with respect to the measures of FFT analysis, regulated output AC voltage waveform, capacitor voltage, and duty ratio. From the evaluation, it is observed that the proposed SVPWM strategy provides the better results with varying frequencies and magnitudes.

In future, the regulated AC output voltage will be extended to remove the high frequency harmonics, because the imbalance condition can be raised due to the small amplitude and high order harmonics.

Disclosure statement

No potential conflict of interest was reported by the authors.


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B. Durai Babu (a) and P. Murugesan (b)

(a) Department of Electrical Engineering, Sathyabama University, Chennai, India; (b) Department of Electrical and Electronics Engineering, S.A. Engineering College, Chennai, India

CONTACT B. Durai Babu [??]


Received 6 May 2017

Accepted 28 January 2018
Table 1. Circuit parameters.

System specification

Parameter                            Value

Input voltage                        100 V
Output voltage                        75 V
Capacitor                            [C.sub.1], [C.sub.2] = 750 [micro]f
Inductor                             [L.sub.1], [L.sub.2] = 75 mH
Nominal frequency                     50 Hz
Nominal phase-to-phase voltage         1 KV
Active power                           1 KW
Inductive reactive power [Q.sub.L]     0
Capacitive reactive power [Q.sub.C]    0
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Author:Babu, B. Durai; Murugesan, P.
Publication:Australian Journal of Electrical & Electronics Engineering
Date:Mar 1, 2017
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