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Selection of frequency dividers for microwave PLL applications.

Selection of Frequency Dividers for Microwave PLL Applications


Direct microwave prescaling for phase locking is an approach where the microwave oscillator frequency is divided down. The division ratio is such that the divided frequency is equal to a stable reference source allowing phase locking. The approach, shown in Figure 1, is technically sound, considering the number of synthesized sources at lower frequencies presently available that incorporate frequency dividers. Direct frequency division for phase locking is not a new idea and follows the trend of high speed digital divider technology.[1-16] By using analog frequency dividers, the technique can be extended upwards in frequency beyond the limits of digital frequency divider technology.

The approach requires no mixers or local oscillators for downconversion to an IF appropriate for digital dividers. Instead a microwave frequency divider chain is used to prescale the microwave frequencies to a point where either conventional programmable digital division can be used for comparison to stable reference, for a single loop synthesizer, or direct comparison to a variable frequency reference, that is, a low frequency loop or a direct digital synthesizer.

The phase noise performance then can be optimized by the selection of the PLL bandwidth to take advantage of very low noise floors offered by fundamental frequency microwave oscillators and the low phase noise of the reference source close to the carrier frequency.[3]

Frequency Divider Requirements

for Phase Locking

When the fundamental VCO operating frequency is higher than the reference frequency, a frequency divider is used to reduce the VCO operating frequency to that of the reference. This is referred to as direct prescaling and is used in PLL synthesizers to generate frequency steps that are integer multiples of the reference frequency. Basic frequency divider requirements for microwave PLLs include high frequency operation, typically up to 26 GHz; broadband operation over an octave bandwidth; variable division ratio; no RF output in the absence of an RF input signal that is unconditionally stable; low cost; low DC power; 50 [OMEGA] input and output; and low insertion loss.

Divider Types

There are two basic types of frequency dividers, analog and digital. These two types of dividers can be broken down into sub-types.

Analog frequency dividers include parametric, subharmonic generation using nonlinear electrical phenomena; oscillator synchronization by subharmonic injection locking; and regenerative or Miller divider using a mixer with feedback.

Less well known analog frequency dividers are based on the properties of traveling space-charge domains in transferred electron devices,[23] the utilization of charge storage phenomena in step recovery diodes[20] and the phase-locked loop frequency divider.

All digital frequency dividers operate on the basic flip-flop divide-by-two principle,[18] and are either dynamic or static.

Dynamic frequency dividers use astable type flip-flops that have a tendency to oscillate in the absence of an input signal due to AC cross couplings and have an operating range that is slew rate limited. Dynamic dividers have AC coupled inputs and typically do not operate to DC.

Static frequency dividers have DC cross couplings and operate to DC. Static dividers provide a stable out-put for each threshold crossing of the input signal triggering edge and remain stable until the next triggering edge; thus the static frequency dividers outputs remain stable in the absence of an input signal.

Divider Technologies

Digital divider technology is best described by the family of logic the dividers belong to. These families include CMOS, TTL, ECL and GaAs. Digital frequency dividers commonly are characterized by their semi-conductor type, typically Si bipolar or GaAsFET or more critically their semiconductor process type.

Parametric frequency dividers operate by subharmonic generation using nonlinear electrical phenomena. Nonlinear reactance devices, such as varactors, are diodes whose junctions are optimized for a voltage-dependent depletion layer capacitance. This capacitance is equivalent to a high-Q nonlinear reactance suitable for frequency division. The discussed commercial analog frequency divider is based on nonlinear reactance devices.

Locked oscillator frequency dividers operate by subharmonic injection locking. Operation of a typical divide-by-two circuit is given. An input signal at the frequency of [] is applied to an oscillator circuit operating at []/2. A frequency pulling phenomenon then locks the two signals together, giving an output at []/2.(12)

The regenerative frequency divider operates with a mixer and feedback. The input signal to be divided is applied to the LO port of a mixer. The IF port then is applied to the RF port to form a feedback loop. With filtering and amplification in the feedback path, division by two is obtained.[9,14,23]


Advantages and Disadvantages

Figures 2 and 3 compare the residual phase noise of various types of frequency dividers. Figure 2 compares residual noise measured at a specific frequency. This data must be normalized to the final operating frequency of the synthesizer to observe the effects on final output spectrum. The digital GaAs divider is noted to be extremely noisy compared to the digital Si dividers and analog parametric dividers. Figure 3 provides a graph of the normalized residual noise levels at 10 GHz. One can conclude that the first dividers in a prescaler chain do not necessarily contribute to the final noise spectrum but rather the low frequency divider noise significantly contributes to the output spectrum. The fast rising slope of the digital GaAs divider is characteristic of the high flicker noise of GaAs devices.[24]

Figure 4 is a comparison of maximum operating frequencies of various types of commercial frequency dividers. 10 GHz is the present limit for digital GaAs dividers,[1] 3.5 GHz is the present limit for Si bipolar frequency dividers[6] and 26 GHz is the present limit for analog parametric dividers.[2] Parametric frequency dividers have been built using finline techniques at 35 GHz.[30] Recently, a commercial 5 GHz bipolar static digital frequency divider was released by Avantek. A 25.4 GHz static digital divider and a 26.6 GHz dynamic frequency divider have been reported. Analog parametric frequency dividers are three times faster than digital GaAs dividers and 10 times fasten than Si bipolar dividers.

Advantages of Analog Parametric

Frequency Dividers

Parametric frequency dividers offer high operating frequencies, the lowest DC power consumption and low residual noise figure. Parametric dividers are reliable, with an MTBF of 350,000 hours for biased devices and 700,000 hours for unbiased devices, and are unconditionally stable.

Advantages of Digital Frequency


Digital frequency dividers are available in monolithic form and have a small package size, division ratios greater than two in a single package, lower noise floor up to 3 GHz in bipolar prescaler chain without amplifiers, and programmable divide ratios.

Disadvantages of Analog

Parametric Frequency Dividers

A disadvantage of analog parametric frequency dividers is that cascading the devices requires amplification between the devices.

Disadvantages of Digital

Frequency Dividers

Disadvantages of digital frequency dividers include high DC power consumption, high flicker noise associated with GaAs dividers and low residual noise Si bipolar dividers limited to frequencies below 3.5 GHz.

Integrated Prescalers

An integrated prescaler is a combination or chain of frequency dividers and conditioning circuits, such as filters, amplifiers, couplers, power dividers and DC bias circuits, packaged in a connectorized enclosure to form a usable function for use in a system or subsystem. Regardless of frequency divider type or technology support, circuits are required to form a usable unit.

Interstage Amplifier Selection

Two sources of noise affect the frequency divider function; the thermal noise floor, which is constant, and the flicker noise, which is frequency dependent, typically less than 1 MHz.

To take advantage of a low noise source, the additive noises of system components must be less than that of the signal of interest.

Conclusions from a Survey

Conducted on Commercial

Frequency Dividers

For a microwave prescaler, an analog parametric frequency divider chain should be used down to 2 GHz and followed by a Si bipolar frequency divider with high output drive capability. The amplifiers should be well matched and the band should be limited to the frequencies of interest. This may include isolators and amplifiers with high reverse isolation.

Phase Noise

and Frequency Dividers

An understanding of how a frequency divider reduces phase noise is required to substantiate the data. The simplest way to explain the noise compression due to division is by narrowband FM modulation theory. Typically, phase noise is understood as a random noise modulating a pure tone resulting in side bands about the carrier. Using Bessel functions of the first kind of argument (B) and order 0 and 1 in conjunction with a known fixed modulation index B, it is possible to predict and measure the relative carrier-to-sideband amplitudes entering and exiting the frequency divider. Figure 5 shows results obtained for the first frequency halver used in a narrowband frequency synthesizer.

Figure 6 shows phase noise tests conducted at the Calibrations and Standards Lab at Communications Security Establishment Ottawa (CSE) on the remaining divider stages used in the narrowband synthesizer.

A Ku-Band Synthesized Source

In order to demonstrate the noise performance of frequency dividers more adequately, a high frequency PLL was constructed. The PLL is accomplished by directly prescaling an 8.96 GHz VCO to 560 MHz for phase comparison with a stable 560 GHz source. A X 1.5 multiplier then was used to produce a 13.44 GHz output signal.

A phase/frequency comparator was used in conjunction with a differential loop filter with an imperfect-integrator-plus-lead-lag function. A third order PLL is formed. The zero frequency was optimum at 88 kHz and the high frequency pole at 603 kHz. For phase noise testing, an HP8662A was used to generate a clean reference signal.

The low cost GaAs FET VCO has a quarter wave resonator and is varactor tuned. This results in a low Q oscillator with poor short term stability and a noisy output spectrum. A wide loop bandwidth was required to suppress the VCO noise. The stabilized noise levels are an improvement over the free running VCO noise over a 200 kHz total frequency span. Figure 7 shows free running VCO spectrum vs. stabilized over a 200 kHz total span.

Measured Synthesizer


The final phase noise performance of the narrowband frequency synthesizer was measured using a phase noise test set with a microwave noise test set in an automated close loop measurement. A graph of SSB phase noise is provided in Figure 8.

The settling time was measured by switching the reference synthesizer by a frequency step and measuring the correction voltage applied to the VCO. A logic analyzer with optional dual trace 50 MHz analog waveform digitizer was used. A fast switching synthesizer was used as the reference for settling time measurement. Figure 9 provides a one-shot trace of digitizer. For a 20 MHz step settling to a phase lock condition was 10 microseconds.


Parametric frequency dividers are low noise, low power dividers that can be used in conjunction with low power bipolar dividers to produce extremely low noise divide chains with maximum input frequencies to 26 GHz. Higher frequencies are in development.

A 13.44 GHz microwave source synthesized by direct division has been developed, built and tested. The source exhibited low phase noise and high stability using a low cost GaAs FET VCO.

Frequency dividers have been and presently are used in frequency synthesis, and will continue to be a critical building block in synthesizers to come. As frequency divider technology advances, analog and digital, so will the applications of dividers to frequency synthesis.


This work has been supported by the Canadian Department of National Defence, Defence Research Establishment Ottawa under contract #05V.W7714-7-5302-SV.

References [1.] NEC Corp. UPG503B Data Sheet, "10 GHz Divide-by-4 Prescaler." [2.] Telemus Electronic Systems Inc., "Frequency Product Guide," June 1988. [3.] Telemus Electronic Systems Inc., AN-1, "Phase Noise and the Parametric Frequency Divider for Phase-Locked Source Applications." [4.] Anadigics Inc., ATB 103, "Microwave Prescaler Maintains Low System Phase Noise." [5.] Gigabit Logic, Inc., "GaAs IC Data Book & Designers Guide," 1988. [6.] Plessey Semiconductors, "Frequency Dividers and Synthesizers IC Handbook," 1988. [7.] Miteq Inc., "Miteq Frequency Sources," Catalog 1988. [8.] K. Osafune, T. Takada, N. Kato and K. Ohwada, "GaAs Ultra High Speed Prescaler/Phase Frequency Comparator Using LSCFL," IEEE Transactions on Microwave Theory and Techniques, Vol. MTT-35, No. 10, October 1987, pp. 917-918. [9.] T. Ohira, T. Hiraoka and H. Kato, "MMIC 14 GHz VCO and Miller Frequency Divider for Low Noise Oscillators," IEEE Transactions on Microwave Theory and Techniques, Vol. MTT-35, No. 7, July 1987, pp. 657-662. [10.] H. Kato, T. Ohira N. Imai and F. Ishitsuka, "A 30 GHz Band Full-MMIC Receiver for Satellite Transponders," IEEE MTT-S International Microwave Symposium, 1988, Vol. 2, pp. 565-568. [11.] H. Ichino, et al., "An 8.7 GHz Si Bipolar Dynamic Frequency 1/64 Divider," IEEE MTT-S International Microwave Symposium, 1988, Vol. 2, p. 568. [12.] P. Dorta, J. Perez and I. Rodriguez, "Digital Radio Link Synthesized With a Direct Division PLL at 22 GHz," IEEE MTT-S International Microwave Symposium, 1988, Vol. 2, pp. 861-864. [13.] Fujitsu Microelectronics, "Prescaler & Phase Locked Loop Data Manual," 1988. [14.] R.H. Derkensen and H. Rein, "7.3 GHz Dynamic Frequency Dividers Monolithically Integrated in Standard Bipolar Technology," IEEE Transactions on Microwave Theory and Techniques, March 1988, Vol. 36, No. 3, pp. 537-541. [15.] M. Madihian and K. Honjo, "GaAs Monolithic ICs for an X-band PLL-Stabilized Local Source," IEEE Transactions on Microwave Theory and Techniques, Vol. MTT-34, No. 6, June 1986, pp. 707-713. [16.] Sony Corp., "Ultra High Speed ECL Standard Logic Family" data sheets. [17.] U.L. Rohde, Digital PLL Frequency Synthesizers Theory and Design, Prentice-Hall Inc., 1983. [18.] W.F. Egan, Frequency Synthesis by Phase Lock, John Wiley and Sons Inc., 1981. [19.] W.P. Robins, Phase Noise in Signal Sources, Peter Peregrinus Ltd., 1982. [20.] V. Manassewitsch, Frequency Synthesizers Theory and Design, 2nd ed. John Wiley and Sons, Inc. 1980. [21.] F.M. Gardner, Phaselock Techniques, 2nd ed., John Wiley and Sons Inc., 1980. [22.] Motorola Inc., MECL Device Data, 2nd ed. 1985. [23.] I. Bahl and P. Bhartia, Microwave Solid State Circuit Design, John Wiley and Sons Inc., 1988. [24.] D. Scherer, "Generation of Low Phase Noise Microwave Signals," RF & Microwave Measurement Symposium & Exhibition, 1981.

PHOTO : Fig. 1 A direct division PPL oscillator.

PHOTO : Fig. 2 Residual noise of various frequency divider types measured at a specific frequency for each type; (a) digital GaAs +4 300 MHz; (b) analog parametric +2 3 GHz; (c) digital S: ECL / 4 125 MHz; (d) digital S: ECL / 4 120 MHz; (e) digital S: ECL / 10 10 MHz; and (f) digital S: TTL / 10 2 MHz.

PHOTO : Fig. 3 Frequency divider residual noise normalized to 10 GHz; (a) digital S: ECL / 10 10 MHz; (b) digital GaAs divided by 4 300 MHz; (c) digital S: TTL divided by 10 2 MHz; (d) digital S: ECL divided by 4 125 MHz; (e) digital S: ECL divided by 4 120 MHz; and (f) analog parametric +2 3 GHz.

PHOTO : Fig. 4 Various types of commercial frequency dividers vs. maximum operating frequency.

PHOTO : Fig. 5 The absolute phase noise of an 8 GHz synthesizer and an 8 GHz halver with output at 4 GHz.

PHOTO : Fig. 6 The absolute phase noise of a 4 GHz synthesizer and a 4 GHz divide by 8.

PHOTO : Fig. 7 The free running VCO spectrum vs. stabilization by phase locking.

PHOTO : Fig. 8 An SSB phase noise of a Ku-band frequency synthesizer measured on an automated phase noise test set with a carrier noise test set.

PHOTO : Fig. 9 The synthesizer loop setting time was measured to be 10 [MU] for a 20 MHz output step.
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Title Annotation:phase-locked loop
Author:Bomford, Mark
Publication:Microwave Journal
Date:Nov 1, 1990
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