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SURVEY OF NETWORK ON CHIP ARCHITECTURES.

Byline: Muhammad Athar Javed Sethi, Fawnizu Azmadi Hussin and Nor Hisham Hamid

ABSTRACT

Network on Chip (NoC) is a communication paradigm for on-chip communication. It has replaced the traditional bus and crossbar interconnection as it has higher bandwidth, modularity, scalability and benefits of resource reuse. This pap er presents the detail survey of the NoC architectures being proposed and implemented in last more than a decade. Apart from comparing the NoC architectures on different parameters, detail information is also provided about these parameters of NoC architecture.

Keywords: Network on Chip (NoC); Routing algorithms; Switching techniques; Clocking mechanism

1. INTRODUCTION

Network on chip (NoC) is a communication framework for multicores connected together in regular or irregular topologies. The various topologies of NoC can be mesh, torus, tree, ring, or it can be a hybrid topology. NoC is constructed from routers, processing elements (PE's), network interface (NI) and interconnects (links). Routers are connected together through interconnects. PE's are connected to routers through NI's. NI separate the data communication of PE's from inter router communication. NI transforms the message generated by PE's to the packet format which router understands. Routers send these packets to the neighbor routers so that it can reach at the destination. PE's can be homogeneous devices or it can be heterogeneous devices. The PE's can be a cache, reconfigurable devices, memory, or any other processing element [1].

Network on chip have replaced the traditional bus based wiring between PE's with a network. In NoC resources are well structured and arranged in a particular topology. This makes the NoC scalable and modular. NoC have higher bandwidth as compared to bus and they support multiple parallel communications. NoC is more organized, it provides efficient utilization of the network resources and have better cost and performance parameters as compared to global wires between PE's [2].

An on chip interconnection network SPIN[3] was proposed in 2000. This put a research foundation for on chip communication algorithm and architectures. Later in 2001, Dally [2] further refined the on chip interconnection network and proposed folded torus based on-chip architecture. The router architect is also explained in this paper. Later, in 2002, Luca Benini named this on chip interconnection network as Network on Chip (NoC) [4]. In this survey paper, various NoC architectures have been reviewed based on the different parameters [1-3, 5-113].

2. Motivation

The purpose of this survey study is to review the existing NoC architectures from different perspectives (parameters). Most of the papers in the literature only review few architectures in their paper and the explanation is specific to their application or domain of the paper. In order to fill the gap and help the research community this survey study is conducted in which more than 100 different NoC architectures are reviewed. This study will help the individuals and researchers about the different characteristics behavior of the NoC architectures. This will help them to find the important and un-resolved issues for further investigation, research and further contribute to the NoC field. To the best of our knowledge, this is the most comprehensive literature review of NoC architectures.

There are few other survey studies on NoC architectures [114-117] but they cover the basic trends, principles and working mechanism of network on chip. These survey studies are not covering the broader spectrum of NoC architectures using various parameters. The survey study [114] is very well written but explains the general trends in NoC research and practices. This survey study only covers eight NoC architectures based on few parameters. The survey study [115] covers sixty eight NoC architectures. The comparison is more qualitative then quantitative. The survey study was published in 2008 and it not up to date. The survey study [116] was published in 2012 and it covers seventy seven different NoC architectures. These architectures are compared based on only four parameters. The parameters include year, switching, topologies and implementation. The survey paper [117] is only covering four NoC architectures using qualitative description.

This paper explains the basic principles of NoC which include routing algorithm, switching, flow control techniques and other mechanisms.

The NoC has brought the tremendous change in the on-chip communication mechanism. It has replaced the traditional wires with the routers and interconnects. The bus between multiple components was not able to cope with communication requirements of them. Scientists come up with the idea of multiprocessors system on chip (MPSoC). This improved the performance of the embedded systems but later, the bus between multi components of embedded systems were not able to cope the heterogeneous and challenging communication requirements of MPSoCs. This leads to the idea of Network on Chip (NoC) by researchers and scientists. The NoC have adapted a lot of difficult and complex concepts of data communication to address the communication requirements between MPSoC [118].

The current literature on the NoC lacks the in depth details of concepts related to this area. This paper is focusing on the parameters which are used by the NoC architectures. The parameters on which the survey study is based on are Link sharing mechanism, Routing algorithm, Connection types, Quality of service (QoS) and Switching techniques.

We believe that the detail information of the parameters along with the real NoC architecture examples will help the research community to know about the current trends in the NoC. This survey paper is also highlighting and gathering the key aspects of NoC from various sources which will act as catalyst for further research.

1. Link Sharing Mechanism:

Link sharing mechanism defined the way how communication channel is shared between multiple sources and destination in NoC. Link sharing mechanisms are basically divided into two broad categories, circuit switching and packet switching (connection oriented and connection less). According to survey study most of the NoC architectures are using packet switching while only few are using circuit switching. Two architectures are using SDM based packet switching technique and other is using WDM for link sharing. This clearly shows the scientists are more interested in effective and efficient utilization of resources as compared to allocating the resources for particular time period. In circuit switching based connections the resources can be underutilized at certain times.

The circuit switching connections also lacks the reactivity to certain rapid changes in the bandwidth and throughput requirements by PE's [3]. In order to efficiently utilize the bandwidth of the NoC, the concept of virtual channels were introduced using time division multiplexing [14], frequency division multiplexing or combination of both these techniques [101]. Despite of these drawbacks of circuit switching technique it is still being used by NoC applications which required guaranteed services [119]. The future link sharing mechanism should include adaptive and hybridize mechanism which can switch between circuit and packet switching based on the traffic load and PE requirement.

1.1 Circuit Switching

In circuit switching a physical link is established between source and destination before data transmission. After the connection establishment flits (flow control digits) or packets traverses the various routers. The connection is established until the all packets are received at the destination [120]. The circuit switching technique is better for high traffic real time applications. These applications generated and send traffic at a higher injection rate. As there is a separate link between source and destination that's why there is no delay communication problem and high throughput can be achieved. In circuit switching technique bandwidth is reserved for entire duration of data but resources (routers, links) are busy until complete data is received at the destination. The setup of path from source to destination increases unnecessary delay [121].

Dally et al.[2], SoCBUS[13], OCN[16], Nexus[21], Wolkotte et. al. [41], PNoC[56], Cross road interconnection architecture[62], Ambric[73], EIB on chip network[75], CSRA-NoC[80] and Ramos et. al.[98] are architectures which are based on circuit switching techniques. Dally et. al. NoC architecture provides virtual channel based circuit switching while OCN provides circuit switching using round robin arbitration. The only drawbacks of the techniques adopting circuit switching are the average utilization of the link. The links are underutilized at certain instant of the time. Therefore, in order to address these issues packet switching must also be used in these systems in order to efficiently utilize the communication channel [12].

1.2 Packet Switching

In packet switching, messages are divided in to packets and flits. The router propagates the flit in a particular direction based on the routing algorithm [122]. Routing algorithm can be deterministic, stochastic, full adaptive and partial adaptive. These routing algorithms are explained in section 2. There are number of architectures which are based on packet switching.

They are CLICHE[1], SPIN[3], aSOC[5], MicroNetwork[6], PROTEO[8], CHAIN[9], RAW[10], Eclipse[11], HERMES[14], SoCIN[17], Nostrum[19, 20], Xpipes[22], R2NoC[23], Spidergon[27], RaSoC[28], QNoC[29], NoCGen[31], Reconfigurable Network on Chip[32], DyAD[33], Asynchronous On chip network router with Quality of Service[35], Black-Bus[36], SNA[37], Topology adaptive NoC[43], Arteris[45], DyNoC[46], Asynchronous NoC Architecture[48], DSPIN[52], INoC[53], XGFT[54], CTNOC[57], Low latency on chip network[58], GEXPolygon and GEXSpidergon[59], CoNoChi[61], Communication Architecture Optimization[66], TILEPro64[70], STNoC[74], SCC[76], MoCRes[77], Generalized de Bruijn Graph NoC[78], Polaris[79], artNoC[81], CDMA NoC[82], A reconfigurable baseband platform based on Asynchronous NoC[83], EVC[85], Aelite[88], XHiNoC[90], Network on Chip in a Three Dimensional[91], BiNoC[92], ALPIN[93], DRNoC[95], PMCNOC[96], Dynamic Reconfigurable Network on Chip[97], WiNoC[101], dAElite[102], BMNoC[103],

Custom Network on Chip Architecture[104], DANoC[105], WaveSync[106], AdNoC[107], Mesh based NoC[109] and BLOCON[112].

1.2.1 Spatial and Wavelength division multiplexing (SDM and WDM)

Spatial division and wave length division multiplexing are link sharing techniques being used by some of the NoC architectures. SDM physically divides every link and buffer into multiple virtual circuits. Every virtual circuit is assigned the portion of the bandwidth. SDM uses the wormhole switching for flow control [123]. An Architecture and compiler for aSoC[24] and Spatial Division Multiplexing NoC[44] are two example of spatial division multiplexing. WDM can send multiple signals simultaneously to attain higher throughput. The wavelength determines the destination address in wavelength division multiplexing or routing. This makes the WDM as contention free link sharing mechanism. ORNoC[99], NoC architectures is providing link sharing using WDM. Some of the architectures have not provided any information regarding their link sharing mechanism.

2. Routing Algorithms:

Routing algorithm defines the path for the packet between source PE and destination PE. There are basically four broad categories of routing algorithms. They are deterministic, stochastic, fully adaptive and partial adaptive routing algorithms. When the routing decision is taken by source it is called source routing while when the immediate nodes of the NoC take the decision then routing algorithm is categorize as distributed routing [14]. The trends of using routing algorithms are that 43% NoC architectures have used deterministic routing algorithm while 19% architectures are using fully adaptive routing algorithms. While none of the NoC architectures have used the stochastic routing algorithm.

Deterministic routing algorithms require fewer resources as compared to adaptive routing algorithm. These algorithms deliver an orderly packet as compared to adaptive routing algorithm. Adaptive routing algorithms provide better throughput and low latency by having alternate paths due to congested or faulty paths. Deterministic and partially adaptive algorithms are deadlock and livelock free while fully adaptive algorithms requires some precaution by having deadlock, livelock and congestion avoiding techniques [119]. Adaptive routing algorithms need special modules at the receiver to reorder the packets, which in turns increases the design complexity and latency of the packets. Deterministic routing algorithms perform well under uniform traffic pattern while adaptive routing algorithms are preferred for bursty and irregular traffic [124]. Few NoC architectures have not specified or it's not clear which routing algorithm they are using.

Scientists have chosen the deterministic routing algorithms because of simplicity as they are less complex to implement.

2.1 Deterministic Routing Algorithms

In deterministic routing the packet routes from the certain point to another using a fixed path. These algorithms lack the adaptiveness. Xy, yx, xyz and zyx [125-131] are few examples of dimension order routing (DOR) algorithms. DOR algorithms are the simplest algorithm of deterministic routing algorithms. These DOR algorithms are deadlock free. In minimal path routing, the packet can traverse using multiple (shortest) paths to reach at the destination. Minimal path routing algorithms are prone to deadlock as compared to DOR [132].

Most of the NoC architectures are based on static and deterministic routing. The NoC architectures are; CLICHE[1], Dally et al. [2], aSOC[5], OCTAGON[7], Eclipse[11], HERMES[14], OCN[16], SoCIN[17], Nexus[21], Xpipes[22], Spider[25], Spidergon[27], RaSoC[28], QNoC[29], DyAD[33], A routing switch for on chip interconnection networks[34], Asynchronous On chip network router with Quality of Service[35], Mango[38-40], Topology adaptive NoC[43], Spatial Division Multiplexing NoC[44], DyNoC[46], Asynchronous NoC Architecture[48], DSPIN[52], XGFT[54], PNoC[56], CTNOC[57], CoNoChi[61], Cross road interconnection architecture[62], HIBI[63], ProtoNoC[67], TILEPro64[70], UT TRIPS[71], SCC[76], MoCRes[77], Polaris[79], artNoC[81], EVC[85], MoCSYS[87], XHiNoC[90], BiNoC[92], DRNoC[95], PMCNOC[96], Ramos et. al. [98], DANoC[105], AdNoC[107], Mesh based NoC[109] and HELIX[113].

2.2 Stochastic Routing Algorithms

Packets are broadcasted in all or particular direction depending on the type of stochastic routing algorithm. The benefits of these algorithms are that they are easy to implement and they are not complex. But the drawbacks of these techniques are that they are not dynamic in nature as the replicate the packets in all direction. They consume high energy and bandwidth. They have deadlock and livelocks problems. These algorithms do not perform well even at low traffic rate. Stochastic routing algorithms provide fault tolerance, adaptability through data redundancy and by eating up the bandwidth of the NoC. Probabilistic gossip flooding scheme, directed flooding, N-Random walk, source routing [125, 126, 133] and connection oriented stochastic routing (COSR) [133] are few examples of stochastic routing algorithm.

2.3 Fully adaptive Routing Algorithms

The routing at fully adaptive algorithms depends upon the routing table or on the routing information collected from the neighbor nodes at router. Based on this information the direction of the packet is decided at run time. Routers constantly communicate with each other to update the routing table or neighbor nodes information. Updating of routing information takes a lot power, energy and time, which affects the throughput of the NoC [125, 134]. Source routing for NoC (SRN) and force directed wormhole routing (FDWR) are two examples of fully adaptive routing algorithm [127, 128]. Fully adaptive routing algorithms are very dynamic but updating of routing information consumes a lot of area, energy and power which sometimes degrade the performance of NoC. The flow of control messages between routers at times creates congestion, deadlock situation in NoC. The techniques [135, 136] are fully adaptive routing algorithm but they does not have the routing table.

They collect the neighbor information through certain control messages. Based on this information, router makes a decision in which direction the packet should be routed.

CHAIN[9], Atthereal[12], BIDI-MIN[15], Mango[38-40], Kavaldjiev et. al.[51], Intel TeraFLOPS[72], Generalized de Bruijn Graph NoC[78], TTNoC[84], Aelite[88] and HT- OCTAGON[89] are few NoC architectures which uses source based routing. While SPIN[3], PROTEO[8], A 0.13m NoC[26], Adaptive Network on Chip[49], A low latency router[50], XGFT[54], High Throughput NoC Architecture[55], GEXPolygon and GEXSpidergon[59], Dynamic reconfigurable NoC for adaptive reconfigurable MPSoC[65], Polaris[79] and DRNoC[95] supports adaptive routing algorithms.

2.4 Partial adaptive Routing Algorithms

Partial adaptive algorithms as the names suggests are partially adaptive. They put some restrictions on the routes which can be taken by router in NoC [14]. These algorithms solve the problem of deadlock and also consume less energy and power as there are no routing tables in it. These algorithms limit the adaptiveness of the NoC and latency of the packets increases due to restrictions [125]. West first, negative first, north last, south last, odd-even and planar adaptive [125, 126, 129-131, 134, 137, 138] are few examples of these algorithms.

artNoC[81], XHiNoC[90], Dynamic Reconfigurable Network on Chip[97], WaveSync[106], Mesh based NoC[109] and SWIFT[111] have turn based adaptive routing algorithms. While RAW[10], Spider[25], NoCGen[31], DyAD[33], Asynchronous NoC Architecture[48], SCC[76], A reconfigurable baseband platform based on Asynchronous NoC[83], XHiNoC[90], BiNoC[92] and Mesh based NoC[109] have odd-even routing algorithms.

2.5 Bio-inspired routing algorithms

Bio-inspired NoC algorithms are a novel way to address the limitations of these traditional NoC algorithms. The idea of bio-inspired algorithms is to take inspiration from the nature to solve the complex and difficult engineering world problems [139]. The bio-inspired algorithm [140] is autonomic by implementing and getting inspiration from the self-configuration, self-healing and self-optimization characteristics of biological immune systems. Two techniques [135, 136, 141] are being inspired by the biological brain robustness and fault tolerance. These techniques have implemented and adopted the self-adapt, self-heal concept of the biological brain in NoC. These bio-inspired techniques have implemented the biological techniques "synaptogenesis" and "sprouting" in NoC to make it fault tolerant and robust. SoCBUS[13], R2NoC[23], Wolkotte et. al.[41], TTNoC[68], WiNoC [101] and dAElite[102] are few NoC architecture which have distributed routing algorithm.

While Nostrum[19, 20] have TDM based deflective routing algorithm. Other NoC architectures are following stream based routing, e-cube routing, Dijsktra shortest path routing, shortest distance, shortest path first and temperature first routing algorithms.

3. Connection Types:

A connection type refers the way source PE is connected with the destination PE. There can be simple or unicast (1-1), narrowcast and multicast connections. Most of the NoC architectures are supporting simple connections by 36% while multicast and broadcast communication types are used by 17% and 3% NoC architectures. Three NoC architectures support broadcast communication while only one architecture supports multipath routing.

The multicast communication produces significant amount of redundant traffic which increases the latency and congestion in NoC as compared to unicast communication. By combining multiple unicast connections, multicast communication can be constructed to overcome the drawbacks of multicast communication. Various MPSoC applications use multicast communication which includes replication, barrier synchronization, cache coherency in distributed shared memory architecture [124].

3.1 Simple connection

1-1, simple or unicast connection is between one source PE and a destination PE [142]. SPIN[3], aSOC[5], OCTAGON[7], CHAIN[9], Atthereal[12], SoCBUS[13], HERMES[14], BIDI-MIN[15], OCN[16], Nostrum[19, 20], Nexus[21], Xpipes[22], R2NoC[23], An Architecture and compiler for aSoC[24], DyAD[33], Mango[38-40], Wolkotte et. al.[41], Arteris[45], Kavaldjiev et. al.[51], DSPIN[52], TTNoC[68], NocMaker[69], UT TRIPS[71], Intel TeraFLOPS[72], EVC[85], Aelite[88], HT-OCTAGON[89], XHiNoC[90], RAMPSoC[94], DRNoC[95], Dynamic Reconfigurable Network on Chip[97], Ramos et. al. [98], Kilo-NoC[100], dAElite[102], BMNoC[103], Custom Network on Chip Architecture[104], DANoC[105], RecMIN[110] and HELIX[113] are few architectures which provide simple communication between PE's.

3.2 Narrow cast connection

Connection between one source PE with one or multiple destination PE's is called narrowcast connection. In narrow cast connection the instruction initiated by the source is only executed by one destination PE. The instruction or data send by the source PE is acknowledged by the return message from destination PE. These connections are bi-directional [142].

3.3 Multi cast connection

Multicast connection is between one source PE with one or multiple destinations PE's such that the instruction/data issued by the source PE is duplicated and the copies are sent to every destination PE. No return messages are allowed from destination PE to source PE in multicast connections due to memory limitations. These connections are uni-directional [142]. These are the architectures which provide multicast connections; CHAIN[9], Atthereal[12], BIDI-MIN[15], Nostrum[19, 20], An Architecture and compiler for aSoC[24], Mango[38-40], HIBI[63], artNoC[81], CDMA NoC[82], EVC[85], Aelite[88], XHiNoC[90], DRNoC[95], Dynamic Reconfigurable Network on Chip[97], Kilo-NoC[100], WiNoC[101], dAElite[102] and BLOCON[112].

3.4 Broad cast communication and multipath routing

In broadcast communication, source PE can send the packets to every destination PE attached with it either directly or indirectly [3]. SPIN[3], Nexus[21] and TTNoC[68] are few architecture which support broadcast communication. Multipath routing uses multiple paths available to route packet from source to destination. CLICHE[1] provides multipath routing. Other NoC architectures have not provided any information regarding it.

4. Quality of Service (QoS):

Guaranteed throughput service (GT/GS) and Best-effort services (BE) are two broad categories of services provided in NoC [120]. Literature shows that most of the NoC architectures are offering BE or packet based QoS. While only few NoC architectures are offering (GT/GS) or both QoS.

4.1 Guaranteed throughput services (GT/GS)

In GS, the resources are reserved for particular instant of time to particular source and destination pair. In GS connection the bandwidth is reserved for guaranteeing the throughput to source destination pair. At times, GS connection can be expensive and it is not utilized properly. Mostly PE's sends the burst of data on these GS connections and then it remains silent for certain period of time. This leads to the underutilization of the communication link. That is why, BE services are also provided along with the GS connection to utilized the unused bandwidth. Video processing is the example of GS connection [12, 143]. Architectures which are providing GS based communication services are aSOC[5], OCTAGON[7], Nexus[21], QNoC[29], Spatial Division Multiplexing NoC[44], PNoC[56], Cross road interconnection architecture[62], HIBI[63], ProtoNoC[67], CDMA NoC[82], TTNoC[84], MoCSYS[87], Aelite[88] and dAElite[102].

4.2 Best-effort services (BE)

Best effort service does not reserve any resource rather it uses the bandwidth unused by the GS connection. BE connections do not provide any guarantee of the bandwidth. BE services connections use the resources efficiently because they are designed for average case scenario as compared to the GS worst case scenarios. Cache updates are the example of BE connections respectively. This implies that GS traffic are used for critical traffic case while BE traffic is used for non-critical traffic [12, 143]. One of the major drawback of the BE services is its unpredictability [144].

CLICHE[1], SPIN[3], Dally et al.[2], MicroNetwork[6], PROTEO[8], CHAIN[9], RAW[10], HERMES[14], BIDI-MIN[15], OCN[16], SoCIN[17], Xpipes[22], R2NoC[23], RaSoC[28], NoCGen[31], Topology adaptive NoC[43], Arteris[45], A low latency router[50], INoC[53], XGFT[54], Low latency on chip network[58], GEXPolygon and GEXSpidergon[59], Low- Power Network on Chip[60], NocMaker[69], TILEPro64[70], UT TRIPS[71], Intel TeraFLOPS[72], SCC[76], MoCRes[77], Generalized de Bruijn Graph NoC[78], Polaris[79], EVC[85], ReNoC[86], HT-OCTAGON[89], XHiNoC[90], Network on Chip in a Three Dimensional[91], BiNoC [92], RAMPSoC[94], DRNoC[95], Dynamic Reconfigurable Network on Chip[97], Ramos et. al.[98], Kilo-NoC[100], WiNoC[101], Custom Network on Chip Architecture[104], DANoC[105], WaveSync[106], AdNoC[107], Mesh based NoC[109], RecMIN[110] and SWIFT[111] are few architectures which provide BE based communication.

4.3 GS and BE services

Router handles both the GS and BE services connections at the NoC. There is an arbitration unit at router which separates the GS and BE connections. The router reads the packet format which has a bit pattern which specifies whether this packet should be sent on GS or BE connections. These packet bits are set by the PE which generates the traffic [12, 145]. Another approach to provide GS and BE services in the NoC is using virtual channels. The high priority virtual channels are used for guaranteed throughput traffic while low priority virtual channels are assigned to BE traffic [146, 147]. There are some NoC architectures which provide both GS and BE based communication. They are Atthereal[12], SoCBUS[13], Nostrum[19, 20], Spider[25], Spidergon[27], Asynchronous On chip network router with Quality of Service[35], Mango[38-40] Wolkotte et. al.[41], Asynchronous NoC Architecture[48], Kavaldjiev et. al.[51], DSPIN[52], artNoC[81] and ALPIN[93].

5. Switching techniques:

Switching techniques refers to control of messages (packets or flits) flow between routers in NoC. It helps the routing algorithm to avoid congestions and conflicts between routers. Circuit switching techniques do not require forwarding strategy as resources are already reserved for them. Packet switching requires forwarding strategy as it have to made decision on per node basis and it requires buffering. In packet switching flits are saved in the router before any routing decision. There are broadly three types of switching techniques, store and forward, virtual cut through and wormhole switching.

The buffering requirement of virtual cut through and store and forward technique is one packet as compared to few flits of wormhole switching. The design complexity of virtual cut through is high as compared to wormhole switching and store and forward technique. The cost (power consumption and area) of wormhole switching is lower as compared to virtual cut through and store and forward technique [144]. At low traffic rate virtual cut through technique has the same low latency as wormhole switching. While at high traffic load the virtual cut through has high throughput as store and forward technique [43]. It is a trade-off between buffering, design complexity and cost for the usages of these switching techniques. 5% NoC architectures are using store and forward flow control technique. While 9% and 48% NoC architectures are using virtual cut through and wormhole switching. This shows the trends in NoC architecture. Scientist and researchers are conscious about the area and latency requirements.

5.1 Store and forward

In store and forward as the name suggests that the packet is completely received at the router and then routing decision is made on it. This increases the latency of the packet and there is more storage requirement at the router [134]. Eclipse[11], R2NoC[23], A 0.13m NoC[26], Black-Bus[36] and ProtoNoC[67] are few architectures which have store and forward flow control.

5.2 Virtual cut through

In virtual cut through flow control, the flit is forwarded to the next router when the neighbor router guarantees that complete packet can be saved. If there is no space in the neighbor router then the complete packet will be saved in that particular router. Virtual cut through router also need buffers to save the complete packet but it has less latency as compared to store and forward technique [14, 134, 144]. When no packets are blocked in the buffers than virtual cut through switching achieves the same latency as of wormhole switching technique in NoC [144]. NoC architectures which have virtual cut through as flow control technique are Star Connected OCN[18], Topology adaptive NoC[43], CoNoChi[61], ProtoNoC[67], MoCRes[77], MoCSYS[87], Kilo-NoC[100], Custom Network on Chip Architecture[104] and Aurora[108].

5.3 Wormhole switching

In wormhole technique packet is divided in to flits. Header, body and tail flits are three broad categories. Header flit contains the routing information while body flit contains the data which is to be transfer from source to destination. Tail flit terminates the communication by informing the routers and the destination. The buffer requirement for the wormhole switching is less as compared to other two techniques. Similarly, wormhole switching has less latency communication requirement as compared to store and forward and virtual cut through [12, 134]. In certain cases the routing and control information are also provided in the packet by allocating few control bits [22]. The drawback of this technique is that when the header flit is blocked in any router all the subsequent following flits of a packet in multiple routers are also blocked. This leads to the deadlock situation in the NoC [144].

Few architectures have separate control lines and other used flow of tokens for flow control between routers [41, 112].

CLICHE[1], Dally et al. [2], SPIN[3], OCTAGON[7], RAW[10], Atthereal[12], HERMES[14], BIDI-MIN[15], SoCIN[17], Xpipes[22], Spidergon[27], RaSoC[28], QNoC[29], NoCGen[31], Reconfigurable Network on Chip[32], DyAD[33], Asynchronous On chip network router with Quality of Service[35], Arteris[45], Asynchronous NoC Architecture[48], A low latency router[50], DSPIN[52], INoC[53], High Throughput NoC Architecture[55], Low latency on chip network[58], GEXPolygon and GEXSpidergon[59], HIBI[63], On chip multimedia Applications[64], Dynamic reconfigurable NoC for adaptive reconfigurable MPSoC[65], Communication Architecture Optimization[66], ProtoNoC[67], TILEPro64[70], UT TRIPS[71], Intel TeraFLOPS[72], EIB on chip network[75], SCC[76], Generalized de Bruijn Graph NoC[78], Polaris[79], artNoC[81], CDMA NoC[82], A reconfigurable baseband platform based on Asynchronous NoC[83], HT- OCTAGON[89], XHiNoC[90], Network on Chip in a Three Dimensional[91], BiNoC[92], DRNoC[95],

Dynamic Reconfigurable Network on Chip[97], WiNoC[101], BMNoC[103], DANoC[105], WaveSync[106], AdNoC[107] and Mesh based NoC[109] are architecture which have adopted wormhole switching as a flow control technique.

5.4 Buffer management

For buffer management between routers, architectures use credit based and share vc control techniques. These techniques help to avoid buffer overflow, packet drop and to have reliable communication between source and destination. At times both these techniques can be used together for controlling the access to the common link. Due to less communication overhead in the shared vc control technique, it consumes less area and power than credit based technique [38].

5.4.1 Credit based buffer management and flow control technique

Credit based flow control technique is employed between adjacent routers and between router and NI. It controls the flow of flits by incrementing and decrementing the credit counter. When ports send a flit it decrements the counter which shows that the port has just send the flit and output port is busy. When the adjacent router receives the flit it sends back the credit message to the router so that it can increase the credit counter. Whenever the credit counter of the output port reaches zero, it cannot send more flits to that particular port [148]. SPIN[3], Spider[25], QNoC[29], Asynchronous on chip network router with Quality of Service[35], TILEPro64[70], UT TRIPS[71], A reconfigurable baseband platform based on Asynchronous NoC[83], Ramos et. al. [98], dAElite[102], BMNoC[103], WaveSync[106] and BLOCON[112] are few architectures which have credit based buffer management and flow control technique.

5.4.2 Share virtual channel (vc) control technique

In share vc control technique there is a share and un-share box counters at source and destination. Whenever a flit is send from the source queue the share box is locked. Now source is not allowed to send more flits until the flit is received at the destination. When the flit is reached at the destination it will toggle the latch of unshared box, which in return sends the unlock signal to shared box via unlock link. This way the source is able to send more flits at the network provided there is no deadlock [38]. Mango [38-40] NoC architecture have adopted the share vc buffer management and flow control technique.

CONCLUSION:

This paper reviews the NoC architectures based on the different parameters. These parameters are link sharing mechanism, routing algorithm, connection types, quality of service, switching technique and NoC clocking mechanism. We believe that this survey will help the research community to have quick glance on the NoC architectures and find the un-resolved issues and contribute further.

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