STARCORE DEBUTS V4 ARCHITECTURE FOR MOBILE MULTIMEDIA.
The StarCore V4 architecture accelerates encoding and decoding of video algorithms, such as MPEG-4, H.264, Windows Media Video 9 (WMV9), and RealVideo, via application-specific instructions and the high level of parallelism of the StarCore variable-length execution set (VLES) architecture. New single-instruction multiple-data (SIMD) instructions allow the V4 architecture to execute up to 54 elemental RISC operations per clock cycle when performing motion estimation, which is a fundamental algorithm common to all video compression standards. As a result, processors based on the StarCore V4 architecture can perform simultaneous software encoding and decoding of VGA-quality MPEG-4 video at 30 frames/second and beyond. As an example, CIF (352 x 288 pixels) video encoding at 15 frames/second requires only about 50 MHz, or 10% of a 500-MHz StarCore V4 processor's computation capability, while video decoding can be performed in less than 20 MHz. This performance is about 60% better than that of previous StarCore processors, whereas power consumption is reduced by up to 50%, resulting in longer battery life in virtually any multimedia product application. Software implementation of video and other multimedia applications provides system integrators with the ability to quickly upgrade their products as soon as new video formats and standards become available.
Easier system integration
The StarCore V4 architecture's improved operating system support and superior code density-which in turn reduces memory cost-facilitates integration into systems-on-chip (SoC). A new memory protection interface eases porting of operating systems onto the architecture and enables programmers to run several concurrent applications safely on the core, thus increasing the robustness of embedded systems and enabling more efficient development and debugging cycles.
The StarCore V4 architecture introduces partial pipeline interlocking and new instructions that make the architecture a better compiler target and improve the density of compiled code. With more software developed in C to target embedded applications, the V4 architecture capitalizes on StarCore's proven VLES technology and an optimizing C compiler to reduce software development cycles and overall system cost.
"The new V4 architecture being introduced by StarCore provides Ittiam with the advantage of a truly efficient compiler/architecture combination. It enables us to write most of our code in C and, with the new multimedia-specific instructions, makes the job of creating compelling new products both simpler and quicker," said Ravishankar Ganesan, VP of Ittiam's multimedia business unit. "The features of the new architecture will result in tighter code, lower cost, and lower power consumption making our products much more appealing to the consumer market."
Freescale Semiconductor, Inc., a wholly owned subsidiary of Motorola, Inc., recently collaborated with StarCore to adopt the architecture for future cellular handset products and communication infrastructure products. The StarCore architecture is currently used in Motorola's MXC platform and 2.5G, 2.75G and 3G handsets. StarCore technology is also used in Freescale's existing communication infrastructure products including their recently announced MSC711X family of DSP products. With higher multi-media performance and tighter code size, the StarCore V4 architecture provides significant advantages for future mobile products.
"The StarCore V4 architecture is ideal for a broad range of consumer electronics devices, including multimedia-enhanced wireless terminals, low-cost E-GPRS and WCDMA handsets integrating single-core wireless modems, and portable video players," said Alex Bedarida, vice president of marketing for StarCore. "The low power consumption and higher code density of StarCore's V4 architecture translate directly into consumer devices with longer battery life and lower weight, while V4's hardware support for optimized video compression and decompression makes low-cost multistandard video recording and playback a reality."
"The enhanced instruction set is designed to closely couple the architecture and compiler, enabling higher code density and even better performance. This makes the new StarCore architecture a better compiler target for Green Hills' MULTI tools. And, with new memory enhancements, V4 has improved support for real-time operating systems," stated Mike Wolf, general manager of advanced products at Green Hills Software.
New Family of StarCore Processors
The StarCore SC2000 family of processor cores will be the first to implement the StarCore V4 architecture. The new processors build on the success of the StarCore SC1000 family of processors. The SC2000 family is based on an efficient six-stage pipeline that is optimized for low power consumption, allowing the processors to operate at frequencies of up to 450 MHz in worst-case 90-nm silicon technology and up to 600 MHz in typical devices, thus broadening the range of applications for StarCore processors.
A dynamic branch prediction circuit eliminates idle cycles during execution of change-of-flow instructions, thereby accelerating new and existing StarCore programs by an average of 10%. In addition, code optimized for the SC2000-family cores will be about 3% smaller than SC1000 code.
Lead customers have already started to design around the new cores. General availability of the SC2000-family cores and platforms is planned for late summer this year.
For additional details about the SC2000-family cores and StarCore V4 architecture, including StarCore contact and intellectual property licensing information, visit http://www.starcore-dsp.com.
Based in Austin, Texas, StarCore is a developer of high- performance processor architectures, cores, and intellectual property building blocks for the communications and consumer electronics industries.
StarCore can be found on the World Wide Web at http://www.starcore-dsp.com.
For more information, call 512/682-8558.
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|Date:||Jul 1, 2004|
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