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SEMATECH Researchers to Present Innovative Results for Cutting-Edge Silicon and Future III-V Channel Transistor Scaling At IEDM.

Papers Reveal Breakthrough Learning and Solutions Critical for Manufacturable Logic and Memory Devices

AUSTIN, Texas & ALBANY, N.Y. -- Demonstrating its leadership in developing alternative transistor materials and processes for next-generation logic and memory technologies, SEMATECH engineers will present five technical papers at the 54th annual IEEE International Electron Devices Meeting (IEDM), the world's premier forum for the presentation of applied research in microelectronic, nanoelectronic and bioelectronic devices, on December 15-17, 2008 at the Hilton in San Francisco, CA.

The papers were selected from hundreds of submissions, and will release new details on cutting-edge research on high -k/metal gate (HKMG) devices, including new advances in reliability, performance and materials understanding for planar and non-planar CMOS technologies.

"Our presence at this year's IEDM once again demonstrates SEMATECH's R&D strengths, our ability to spearhead innovation, enhance fundamental understanding and our focus on cost-effective manufacturing solutions in a materials driven scaling era," said Raj Jammy, SEMATECH's vice president of materials and emerging technologies. "Throughout the week, the semiconductor device community will have the opportunity to hear our technology experts describe the work we're doing for our members and the industry on new materials for transistor scaling."

Additionally, SEMATECH will host an invitational pre-conference workshop entitled "III-V CMOS on Si: Technical and Manufacturing Needs" on December 14. The workshop will focus on technical and manufacturing challenges affecting the use of III-V materials in CMOS devices. Co-sponsored by Aixtron AG, the workshop will include experts from Industry and Academia debating on the challenges and opportunities of III-V leading to an early understanding of key issues in the large-scale manufacturing use of elements in columns III, IV and V of the periodic table.

Experts from SEMATECH's Front End Processes (FEP) Division will present research results at the following sessions:

* Session 2, Monday, Dec. 15 at 2:25 p.m.: Device and Reliability Improvement of HfSiON+LaOx/Metal Gate Stacks for 22nm Node Application - demonstrates an advanced gate stack for 22nm LOP application. PBTI and mobility degradation issues of low Vt HfSiON+LaOx gate stack are addressed by the optimization of process sequence, LaOx cap thickness and SiON IL.

* Session 5, Monday, Dec. 15 at 2:25 p.m.: A Comprehensive and Comparative Study of Interface and Bulk Characteristics of nMOSETs with La-Incorporated High-k Dielectrics - reveals that HfLaSiON has a strong relationship with the interface characteristics and barrier height, while HfLaON with the bulk trap characteristics. This work was done in collaboration with researchers from Chungnam National University.

* Session 5, Monday, Dec. 15 at 2:50 p.m.: The Impact of La-Doping on the Reliability of Low Vth High-k/Metal Gate nMOSFETs Under Various Gate Stress Conditions - reports results of a comprehensive reliability study for La-doped HfSiO dielectrics using PBTI, TDDB and flicker noise.

* Session 15, Tuesday, Dec. 16 at 9:05 a.m.: Addressing The Gate Stack Challenge For High Mobility InxGaAs Channels For NFETs - This collaborative work (between Intel, SEMATECH, University of Texas Austin, SUNY Albany, Stanford, and University of Oklohoma), addresses key gate stack issues including a) EOT scalability for high performance and electrostatic control with acceptable leakage at operating and off-state, b) understanding the impact of charge trapping, c) thermal stability on InGaAs, and d) the impact of In% on interface on surface channel MOSFETs.

* Session 32, Wednesday, Dec. 17 at 10:45 a.m.: Breakdown in the Metal/High-k Gate Stack: Identifying the "weak Link" in the Multilayer Dielectric - demonstrates that the interfacial layer is the major factor controlling the overall degradation and breakdown of the gate stacks in inversion. Defects contributing to the gate stack degradation are associated with the high-k/metal -induced oxygen vacancies in the interfacial layer.

The IEDM is the flagship conference of the Electron Devices Society of the Institute of Electrical and Electronics Engineers (IEEE). The conference spotlights leading work in more areas of the field than any other conference, annually drawing some 2,000 of the world's top electronics scientists and engineers. It is one of many industry forums SEMATECH uses to collaborate with scientists and engineers from corporations, universities and other research institutions, many of whom are research partners.


For 20 years, SEMATECH[R] (, the global consortium of leading semiconductor manufacturers, has set global direction, enabled flexible collaboration, and bridged strategic R&D to manufacturing. Today, we continue accelerating the next technology revolution with our nanoelectronics and emerging technology partners.
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Publication:Business Wire
Date:Dec 9, 2008
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