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Review of 2.4 GHz-band digital receivers for Zigbee applications.

1 INTRODUCTION

Zigbee has increasingly attracted research interest. Zigbee is a low-data-rate, low-power, and low-cost wireless networking protocol based on the IEEE 802.15.4 standard for wireless personal area networks (WPANs) [1]. The standard specifies that wireless devices operate in the 2.4 GHz frequency band with data rate of 250 kbps [2]. The transmission range is 10-100 m, based on the environment [3]. Li and Zhang [4] mentioned more than 100 well-known global coalitions of hardware and software companies committed to the development of Zigbee technology for various applications. These applications include wireless sensor networks, home automation, remote control, industrial automation, agricultural automation, and medical care.

Two main type of Zigbee networking topologies are star and peer-to-peer. In the star topology, every device in the network can communicate only with the personal area network (PAN) coordinator. A FFD takes up a role as PAN coordinator, the other nodes can be RFDs or FFDs. In the peer-to-peer topology, each device can communicate directly with any other device if the devices are close enough together to establish a successful communication link. Any FFD in this topology can play the role of the PAN coordinator.

The IEEE 802.15.4 defines four MAC frame structures: beacon, data, acknowledgment, and MAC command frames. The beacon frame is used by a coordinator to transmit beacons. The function of beacons is to synchronize the clock of all the devices within the same network. The data frame is used to transmit data. Meanwhile, the acknowledgement frame is used to confirm successful frame reception. The MAC commands are transmitted using a MAC command frame.

For this standard, 16 channels are available with ample channel spacing of 5 MHz. A direct-sequence spread spectrum (DSSS) (Table 1) with a digital spreading function representing pseudorandom noise (PN) chip sequences is employed [5]. An offset quadrature phase-shift keying (OQPSK) completes the Zigbee function. The OQPSK processes the I-channel signal with the Q-channel signal, which is delayed by half a cycle to avoid sudden phase-shift changes [6]. Figure 1 shows the structure of the physical protocol data unit (PPDU) packet format based on IEEE 802.15.4 standard [7]. The preamble field contains 32 bits of "0" for packet detection and synchronization in the receiver. The start of frame delimiter (SFD) field denotes the start of the packet data, which comprises 8 bits of data. The combined preamble and SFD form the synchronization header (SHR). The physical header (PHR) contains the frame length field that indicates the octet number of the physical layer service data unit (PSDU). This field is 7 bits in length, with 1 bit reserved. The PSDU field has a variable length and carries the physical packet data. The SHR, PHR, and physical (PHY) payload form the PHY packet known as the PPDU.

Various studies have designed digital receivers using different methodologies, such as with Matlab, VHDL, and schematic. However, Matlab can only be used for modeling and simulation. Schematic is not practical when the circuit is more complex because the method needs a longer design timeframe. This leads to the behavioral modeling of digital design through VHDL, which is more time-efficient than other methods. Most importantly, the VHDL code can be simulated and implemented directly on field-programmable gate array (FPGA) as a prototyping device, or on an application-specific integrated circuit (ASIC). At present, FPGA is well known for real-time design verification before implementation on ASIC. This may be due to the FPGA characteristics that enable low cost production, faster verification, reconfiguration, composition of millions of system gates, and the latest combination with advanced 28 nm technology process [8, 9]. This is almost similar to ASIC's characteristic. Meanwhile with ASIC, researchers can justify designs with a very small core area in square millimeters. This is invaluable in the current industrial technology need for a compact and very small chipset. However, ASIC involves numerous design steps and longer timeframe.

Previous works on Zigbee digital receiver designs are referenced in the literature survey.

2 LITERATURE SURVEY

Only a few researchers concentrate on digital receivers, compared with analog/RF receivers, for Zigbee applications. Di Stefano et al. [10] designed a simple receiver architecture using Matlab, Simulink, and VHDL as shown in Figure 2. The architecture only involves four blocks, and this design was implemented on Spartan3-200 FPGA. A 1 MHz low-pass filter reduces signal noise and co-channel interferences. The noncoherent OQPSK demodulator functions as a phase detector. The correlator and bit-timing block retains the original code and acquires timing and phase reference during the reception of each frame preamble. The frame-processing block then decodes the data field before sending to the MAC or host. The Zigbee configuration requires less than 200 slices at 22 MHz sampling frequency.

Shuaib et al. [11] developed Matlab Simulink models for Zigbee protocols and the performance evaluation for these models. The generic model includes a spreader, a despreader, a modulator, a demodulator, and an additive white Gaussian noise (AWGN) channel. At the receiver, the obtained 32 bits are sent to the despreader, which reverts them to integers. Then, the integer-to-bit converter changes the received integer to a 4-bit stream before the comparison with original data. The bit error rate (BER) is also calculated. Simulations were performed to study the BER versus signal-to-noise ratio (SNR) of the designed models at different communication parameters. A higher data rate caused a higher error probability for a desired SNR.

[10]

Meng et al. [12] proposed the digital receiver architecture for Zigbee applications as illustrated in Figure 3. The architecture comprises six blocks: carrier synchronizer, IF downconverter, filter, quadrature demodulator, chip synchronizer, and despreading. The IF downconverter changes IF signals from the ADC to the Iphase, earlier I-phase, later I-phase, and Q-phase signals. The filter block determines the phase offset between the carrier and local oscillator. The quadrature demodulator then removes the phase offset. The chip synchronizer synchronizes the I-Q signals. The despreading block recovers the bits after the correct chip synchronization is obtained. This receiver was designed with VHDL and implemented on Xilinx Virtex-4 LX60 FPGA. The configuration obtained: 3,047 slices out of 26,624; 3,659 flip-flops out of 53,248; 4,125 four-input LUTs out of 53,248; and 24 multipliers out of 64.

Kim et al. [13] successfully designed and fabricated a low-complexity demodulation scheme for Zigbee receiver with 0.18 iam CMOS standard cell library. In this scheme, multiple active correlators for demodulation are replaced with a matched filter-based cross-correlator. The demodulator shares correlators with a synchronization unit, which requires only a few additional control units. With this correlator sharing, the total complexity can be reduced. The proposed receiver reduces 36 nontrivial multipliers to 6; 338 adders to 259; and 59 K to 27 K logic gates over the existing hardware architecture from IEEE Std.802.15.4 [14].

[12]

A different architecture of Zigbee receivers was designed and fabricated by Chen and Ma [15] using TSMC 0.18 um technology process. The architecture is as shown in Figure 4. The receiver works in three steps: packet detection, synchronization, and data recovery. At the packet-detection stage, other blocks are turned off until the packet is detected. At synchronization, the carrier frequency synchronization block is turned on to estimate frequency error by preamble, and the phase compensation block works for phase rotation. The despreading block collects the packet information. Finally, at the data-recovery stage, symbol-to-bit block recovers the data bit stream for media access control (MAC). The phase-tracking block begins to track the phase error. In the present paper, the packet error rate (PER) can achieve 0.01 at SNR lower than 5 dB. This design has a chip area of 1.63 x 1.63 [mm.sup.2] which including transmitter and receiver, with a gate count of 78 k.

Bernier et al. [16] designed an ultra low-power Zigbee digital receiver using 130 nm CMOS technology process, as shown in Figure 5. The 4 MSps 3-bit I/Q streams are half-sine-filtered before feeding to the synchronization block and the decoding module. The synchronization block recovers the symbol clock using a code matched filter and a recursive channel filter. The code-matched filter is implemented by eight partial correlation banks. The recursive channel filter increases the SNR by averaging samples over symbol periods. The SFD then locks the symbol clock, and the required symbol correlations are performed for each symbol period. The sample stream is decimated by a factor of 2, which means that a single complex sample per chip is retained. At 1.2 V, the design drains 5.4 mW in receiver active modes and achieves 1% PER for a -81 dBm input power.

[15]

[16]

Zhang et al. [17] designed the digital receiver using six blocks with Matlab and CoWare's signal processing designer (SPD), as depicted in Figure 6. The blocks comprised of chip recoverer, chip synchronizer, received-signal strength indicator (RSSI), I-Q channel detector, bit synchronizer, and symbol recoverer. The chip recoverer regains the two chip streams from the I-Q input signals. The chip recoverer is controlled by a chip synchronizer for aligning the chips. Then, RSSI detects the presence of a valid input signal. The I-Q channel detector identifies the Q-channel chip stream between the two chip streams and locates the bit stream head. The I-channel chip data is ignored to simplify the receiver implementation. Only the Q-channel chip data is used to extract the bit data by a bit-synchronizer module. Finally, the bit data is processed into symbol data by a symbol recoverer. The receiver was implemented on an element computing array (CXI ECA-64) platform, which delivers faster reconfiguration time and higher-computational-density FPGAs with similar computational power. Final results show that 84% represents logical operations used, with 18% of the memory units implementing delay functions and shift registers.

Figure 7 shows the architecture of digital receiver for 2.4 GHz band that was designed by Wang et al. [6, 18]. The authors not only implemented the receiver on FPGA, but also fabricated the receiver using 0.18 iam CMOS technology process. The architecture is quite complicated, and involves eight blocks. The packet detector discriminates whether the incoming signal is data or noise. The phase difference detector finds the phase difference of each sample data. The downsampling block finds the maximum phase difference, and performs the downsampling. Meanwhile, the frequency-offset compensation computes and compensates the frequency offset. The noncoherent demodulator uses the minimum shift-keying (MSK) scheme to perform the demodulation process. The MSK is believed to be similar to OQPSK. The preamble removal block acquires and removes the preamble from the PPDU packet. The despreading block despreads each chip PN sequence to the symbol data. The confirm SFD block acquires the PSDU length and notifies the MAC layer of the PSDU obtained from the receiver. All the process corners (0 [degrees]C, +100 [degrees]C) and (SS, TT, FF) models were simulated to verify the design. The fabrication results shows that the PER is less than 1% at 8 MHz system clock.

The design methodologies and measurement results of all the eight papers for the past five years are summarized in Table 2 for comparison.

[6,18]

3 CONCLUSION

Various designs of digital receivers for 2.4 GHz Zigbee applications and the experimental results performed in the last five years have been summarized in the current review. Two observations were derived. The first observation is that a simpler digital receiver architecture uses a smaller amount of logic gates. This was shown by Di Stefano at al. [10], who designed the simplest receiver architecture using Matlab for optimization before coding with VHDL for FPGA implementation. Second, ASIC implementation showed that the sampling frequency and power supply used are much lower than that of FPGA. This is important in avoiding loss of signal integrity. The signal integrity loss may be due to the rise and fall times of output signals, which decrease because devices are designed to operate faster and use smaller silicon manufacturing process. Moreover, with ASIC, the receiver can be designed to obtain a minimum core area and very low power consumption. This is a very important characteristic of Zigbee applications, as proven by Wang et al. [18].

According to the literature reviewed, each paper has its own advantages and disadvantages. Hence, improving the design of Zigbee digital receiver is intended in the near future. A very simple receiver architecture will be designed and implemented on FPGA with a low sampling frequency to obtain an optimized design and time efficient methodology.

ACKNOWLEDGEMENT

This research received financial support provided by Universiti Sains Malaysia Short-term Grant No. 304/PCEDEC/60312004.

REFERENCES

[1.] Kluge, W., Poegel, F., Roller, H., Lange, M., Ferchland, T., Dathe, L. and Eggert, D., "A fully integrated 2.4 GHz IEEE 802.15.4-compliant transceiver for Zigbee applications", IEEE Journal of Solid-State Circuits, 41, 12(2006), 2767-2775, doi:10.1109/JSSC.2006.884802.

[2.] Farahani, S., "Zigbee wireless networks and transceivers", Newnes Press, USA, 2008.

[3.] Lee, J.S., Su, Y.W. and Shen, C.C., "A comparative study of wireless protocols: Bluetooth, UWB, Zigbee and WiFi", Proceeding of the 33rd Annual Conference of the IEEE Industrial Electronics Society (IECON), 2007, 46-51, doi:10.1109/IECON.200704460126.

[4.] Li, Y. and Zhang, K., "Research on application of Zigbee technology in flammable and explosive environment", Scientific Research, Wireless Sensor Network, 2 (2010), 467-471, doi: 10.4236/wsn.2010.26058.

[5.] Oualkadi, A.E., Anderdorpe, L.V. and Flandre, D., "System-level analysis of O-QPSK transceiver for 2.4 GHz band IEEE 802.15.4 Zigbee standard", Proceeding of 14th International Conference on Mixed Design, 2007, 469-474, doi: 10.1109/MIXDES.2007.4286206.

[6.] Wang, C.C., Huang, J.M., Lee, L.H., Wang, S.H. and Li, C.P., "A low-power 2.45 GHz Zigbee transceiver for wearable personal medical devices in WPAN", 2007, 10.2-5, available at: http://ieeexplore.ieee.org/ie15/4145986/4099325/04146217.pdf .

[7.] IEEE Std.802.15.4, "Part 15.4: Wireless medium access control (MAC) and physical layer (PHY) specifications for low-rate wireless personal area networks (LR-WPANs)", 2006, 42-48, [c]2006 IEEE.

[8.] Crow, G., "Designing digital displays with FPGA", ECN Asia Magazine, July 2008, 3031.

[9.] McGrath, D., "Xilinx confirms: Samsung, TSMC in, UMC out at 28-nm", 2010, available at: http://www.eetimes.com/electronics-news/4087890/Xilinx-confirmsSamsung-TSMC-in-UMC-out-at-28-nm.

[10.] Di Stefano, A., Fiscelli, G. and Giaconia, C.G., "An FPGA-based software defined radio platform for the 2.4 GHz ISM band", 2006, 73-76, available at: http://ieeexplore.ieee.org/stamp/stamp.isp?arnumber=01689899.

[11.] Shuaib, K., Anuaimi, M., Boulmalf, M., Jawhar, I., Sallabi, F. and Lakas, A., "Performance evaluation of IEEE 802.15.4: Experimental and simulation results", Journal of Communications, 2007, 2(4), 29-37, doi: 10.4304/jcm.2.4.29-37.

[12.] Meng, T., Zhang, C. and Athanas, P., "An FPGA-based Zigbee receiver on the Harris software defined radio SIP", Proceeding of the SDR 07 Technical Conference and Product Exposition, (http://groups.winnforum.org/p/cm/ld/fid=57), Denver, Colorado, 2007, 1-5.

[13.] Kim, W., Jung, Y., Lee, S. and Kim, J., "Low complexity demodulation scheme for IEEE 802.15.4 LR-WPAN systems", IEICE Electronics Express, 2008, 5(14), 490-496, doi: 10.1587/elex.5.490.

[14.] IEEE Std.802.15.4, "IEEE standard for wireless medium access control (MAC) and physical layer (PHY) specifications for low-rate wireless personal area networks (LR WPANs)", 2003, 40-50, [C]2003 IEEE.

[15.] Chen, K.H. and Ma, H.P., "A low power Zigbee baseband processor", Proceeding of 2008 International SoC Design Conference, 2008, 40-43.

[16.] Bernier, C., Hameau, F., Billiot, G., de Foucauld, E., Robinet, S., Lattard, D., Durupt, J., Dehmas, F., Ouvry, L. and Vincent, P., "An ultra low power SoC for 2.4 GHz IEEE802.15.4 wireless communications", 2008, 426-429, doi: 10.1109/ESSCIRC.2008.4681883, available at: http://ieeexplore.ieee.org/xpls/absall.isp?arnumber=4681883&tag=1.

[17.] Zhang, C., Athanas, P.M., Reed, J.H., Martin, T.L. and Buehrer, M.R., "An ECA-based Zigbee receiver", Thesis for Master of Science in Electrical Engineering, Virginia Polytechnic Institute and State University, Virginia, 2008.

[18.] Wang, C.C., Sung, G.N., Huang, J.M., Lee, L.H. and Li, C.P., "A low-power 2.45 GHz WPAN modulator/demodulator", Microelectronics Journal, 41(2010), 150-154, doi: 10.1016/j.mejo.2010.01.012.

Rafidah Ahmad and Othman Sidek

Collaborative Microelectronic Design Excellence Centre (CEDEC), Engineering Campus, Universiti Sains Malaysia, 14300 Nibong Tebal, Penang, Malaysia

rafidah.ahmad@usm.my, othman.cedec@usm.my

Table 1. Symbol-to-chip mapping using DSSS [7]

Data               Data            Chip Values
symbol            symbol           ([c.sub.0], [c.sub.1] ...
(dec.)            (bin.)           [c.sub.30], [c.sub.31])
          ([b.sub.0], [b.sub.1],
          [b.sub.2], [b.sub.3])

0                  0000            11011001110000110101001000101110
1                  1000            11101101100111000011010100100010
2                  0100            00101110110110011100001101010010
3                  1100            00100010111011011001110000110101
4                  0010            01010010001011101101100111000011
5                  1010            00110101001000101110110110011100
6                  0110            11000011010100100010111011011001
7                  1110            10011100001101010010001011101101
8                  0001            10001100100101100000011101111011
9                  1001            10111000110010010110000001110111
10                 0101            01111011100011001001011000000111
11                 1101            01110111101110001100100101100000
12                 0011            00000111011110111000110010010110
13                 1011            01100000011101111011100011001001
14                 0111            10010110000001110111101110001100
15                 1111            11001001011000000111011110111000

Table 2. Comparison of design methodologies and measurement
results among previous works

Specification          [10]       [11]        [12]          [13]

Design               ANSI C,     Matlab       VHDL     0.18 [micro]m
approach               VHDL                                 CMOS

Simulation           Matlab,    Simulink     Xilinx          NA
                      Xilinx

Implement.             FPGA        NA         FPGA          ASIC

Clk freq.             22 MHz       NA        48 MHz          NA

Power
Consumption             NA         NA          NA            NA

Slice (%)               10         NA          11          -54 *

LUT (%)                 NA         NA          7             NA

Multiplexer
(%)                     NA         NA          37          -83 *

Power
supply (V)              5          NA          4             NA

Core
area ([mm.sup.2])       NA         NA          NA            NA

Specification             [15]             [16]

Design               0.18 [micro]m    0.13 [micro]m
approach                  TSMC             CMOS

Simulation                 NA               NA

Implement.                ASIC             ASIC

Clk freq.                4 MHz            8 MHz

Power
Consumption             1.719 mW          5.4 mW

Slice (%)                (78 k)           (30 k)

LUT (%)                    NA               NA

Multiplexer
(%)                        NA               NA

Power
supply (V)                1.8              1.2

Core
area ([mm.sup.2])         1.13              4

Specification          [17]          [18]

Design               Matlab,    0.18 [micro]m
approach               SPD           CMOS

Simulation            Matlab        Xilinx

Implement.             CXI          FPGA,
                      ECA-64         ASIC

Clk freq.               NA          8 MHz

Power
Consumption             NA          641 [micro]W

Slice (%)               NA            NA

LUT (%)                 84            NA

Multiplexer
(%)                     25            NA

Power
supply (V)              NA           1.8

Core
area ([mm.sup.2])       NA           0.39

* Reduced over the existing hardware architecture.

Figure. 1. PPDU packet format.

                                     Octets

                                 1               variable

                   Frame length     Reserved
Preamble    SFD      (7 bits)       (1 bit)        PSDU

        SHR                     PHR             PHY payload
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Author:Ahmad, Rafidah; Sidek, Othman
Publication:International Journal of Emerging Sciences
Article Type:Report
Geographic Code:9MALA
Date:Jun 1, 2013
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