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Repeatably fabricating copper channels for 10 Gb/s NRZ signaling: a statistical approach for characterizing system performance and variation for 10 Gb/s channel designs.

Thanks to advances in silicon and passive interconnect technologies, which have made achievable 10 Gb/s data transmission in copper, the buzz around 10 Gb/s backplane systems has grown significantly over the past 12 months. Many markets are actively looking at 10 Gb/s passive channel designs for next-generation equipment. Interconnect Technologies and Winchester Electronics (both divisions of Northrop Grumman Corp.), and Xilinx jointly designed and manufactured a full reference design, based on the ATCA mechanical footprint, running at 10G/s serial data (NRZ) with eight crosstalk aggressors. This first step proves that 10 Gb/s can be achieved, while managing silicon costs and power consumption when proper design and simulation are performed on the passive layer.

However, there is still a hurdle to cross: Process variance during fabrication and environmental conditions of operation can have a significant impact on channel performance. Therefore, it is crucial to understand the sources of variation and how they affect the channel's critical-to-function electrical parameters.

The complexity of channel design increases exponentially as designers confront the 10 Gb/s challenge. This is because at 5 GHz, backplane channels take the form of microwave waveguides, and the fundamentals of RF design come into play. As a result, the interaction of channel components (such as connectors and transmission lines) becomes very important. In fact, the impact of the connector launch and PCB via structures throughout the entire passive channel has the largest degradation on signal performance. These interactions must be carefully managed to minimize channel loss and noise.

S-parameters provide a common framework for describing electrical performance of complete channels and their components. Unfortunately, S-parameters are complex numbers and are difficult to interpret. Most commonly, the magnitude of the S-parameter at the fundamental frequency is used to describe the performance of an interconnect channel or one of its components. The signal power over the channel noise is the signal-to-noise ratio (SNR). The SNR is a driving parameter for receiver technology. For a 12" channel, the sources of loss and noise and their magnitudes are given in TABLE 1.

A perfect passive channel would exhibit zero loss or noise. However, that is not reality. From Table 1 it is possible to understand the relative magnitudes of the losses and noise that different channel components contribute. Focusing on the board technologies, the table also shows that there are several areas within the PCB to improve these signal integrity degradations. There are two PCB technologies that most significantly enable 10 Gb/s channels.

Via design is the first PCB enabler of clean passive channels for high-speed applications. Impedance mismatches in the channel cause power loss through signal reflections. To address this, care must be taken to tightly control PCB and connector impedance tolerances. But the dominant cause of impedance mismatch problems is the connector launch, where conventional via structures can produce up to -30 Db loss in a channel due to stub effects, which are in turn caused by signal ringing in the barrel of plated through-holes.

The good news is that this is relatively easy to fix. Back-drilling removes the stub and has become a very effective solution for signal integrity improvement and typically does not add significant cost. (1)

Via tuning is also effective in managing the impedance mismatch in the via. Through simulation, via pads and antipads can be optimized to ensure the desired impedance is maintained, thus further reducing the negative effects of the via. This effectively means every via must be treated as an individual component and requires diligent design and simulation.

The bad news is that the opportunity to use smaller vias and to tune them is dictated by the connector. Traditional 2 mm grid-type connectors, for example, that use conventional press-fit terminations are challenging due to the limitations on maximum antipad size caused by the required via dimensions.

The other key enabler of the 10 Gb/s passive channel is the dielectric material. Transmission line losses are dominated by material dispersion and skin effect, which contribute 5 dB between them. These are directly proportional to the length of the transmission path. Use of a lower-loss material (low Dk and Df) has a significant effect on channel loss. A designer has very little control over loss beyond the material choice, assuming efficient layout practice. However, material choice always requires a cost/benefit analysis, as high performance materials come at a premium. This analysis must consider all aspects of the channel to ensure there is proper margin in the design, (discussed later in more detail).

Channel crosstalk must also be carefully managed. Common-mode noise rejection in differential-pair PCB transmission lines means little attention is required in this area beyond good layout practice. However, internal connector crosstalk and crosstalk in the via field of the connector launch need to be analyzed carefully.

Inductive coupling between adjacent differential pairs causes crosstalk in the connector launch vias. The magnitude of this problem is entirely a function of the selected connector, since it is the connector footprint that determines the position of adjacent differential pairs relative to each other. If the footprint permits, it is possible to manage via field crosstalk through good design practice.

The decisions made during architecture definition will determine the level of flexibility in the channel design. While there are several components available that may work in a 10 Gb/s channel, it is important to understand how these components will affect other channel components and their interactions.

These 10 Gb/s channel enabling techniques have recently been shown to he effective. Northrop Grumman's Winchester Electronics and Interconnect Technologies collaborated with Xilinx to produce the first full reference design based on the ATCA mechanical footprint running 10 Gb/s NRZ signaling. The system was designed, simulated and validated. The objective of this project was to demonstrate that, with thorough design and simulation, a 10 Gb/s system could be built. The key architecture components were the Xilinx Virtex II ProX FPGA, a Winchester Electronics SIP1000 connector and the circuit boards. Using NRZ signaling, data were transmitted over two daughtercards and the backplane with the eight most significant crosstalk aggressors active. The longest channel length was set for 40", as would be required from the CEI 11G LR objective from the OIF.

Performance Issues

These key technologies and design techniques help ensure that under normal conditions 10 Gb/s NRZ channels will operate successfully. While these technologies and techniques are extremely important and very complex, they are only the start. Ultimately, the design objective is to have repeatable channel performance across thousands of systems with thousands of channels in operation. This adds a new level of complexity. Interconnect Technologies has a novel metrology--a statistical process--to ensure robust, repeatable channels.

Two fundamental issues can undermine a well designed channel. First, process variation during fabrication will change the electrical characteristics of the passive channel, thus affecting performance. Second, environmental variations on channels operating in the field will affect channel performance. Many fabricators and designers are just beginning to uncover the performance issues that may arise and how degradation of the channel can occur unexpectedly, to the point of failure. The fabrication of printed circuits involves many process steps. In current designs, fabrication tolerance affects the design process only during the layout phase to ensure the board will be manufacturable. However, that is not enough at 5 GHz. The channel variation must be analyzed relative to the critical to function electrical parameters associated with the system architecture, not just the fabrication capability. Therefore, it is essential to consider these aspects very earl), in the design process as the risk of failure will have an effect on channel design choices, such as active signaling improvements, interconnect, via design and material choice.

Process variations impact channel performance as they typically exhibit Gaussian distribution properties. As described previously, the via and transmission line design are critical to performance and manufacturability. These aspects are equally important in repeatability. There are at least 16 different processes involved in the fabrication of the via and transmission line, with each process having an associated tolerance. Process variance such as drill wander is typically analyzed to ensure that the product will not violate annular ring or tangency requirements and break out of the copper pad, thus causing an open or short. Drill wander may not appear to affect electrical performance provided there are no shorts or opens. However, at 5 Ghz, drill wander will change the feature of the pad and antipads around the signal via. Because the shape of pads and antipads have a great impact on the capacitive fields of the signal as it moves through the via, the impedance will change. As described, an impedance mismatch win cause reflections and thus increase the channel loss.

The significance of each source to channel performance varies. As shown in FIGURE 1, as the Dk of a material varies about 0.2, the impact to $21 is about 0.2 dB. This Dk variance is typical of what fabricators see when reviewing different laminate lots.

[FIGURE 1 OMITTED]

At first glance, 0.2 dB does not appear significant, but when considering all the variables together over a number of systems, the channel performance can degrade beyond the point of receiver sensitivity. Each variation impacts the critical-to-function electrical parameters associated with the channel performance.

Designers must also consider the system environmental requirements when designing a 10 Gb/s channel. While systems have long received stringent environmental testing prior to field installations, the channel degradation at 5 GHz is surprising to many. RF designers for antenna applications and outdoor systems have long considered the environment. However, this variation may be new to many digital system designers.

All these aspects are critical in the design of high-speed channels. While many understand the tolerances associated with fabrication tolerance, the impact to electrical channel performance is not well understood in the industry. It is essential during architecture definition to assess channel margin relative to these variations. This shift in design philosophy will truly ensure robust channel design over the life cycle of the product.

In 10 Gb/s backplane systems, connector and PCB specifications can no longer be considered separately since they become mutually interdependent technologies: connector performance depends upon PCB termination and PCB performance depends upon connector footprint. When entering into a 10 Gb/s backplane design project, partner with a company that understands how both connector and PCB technologies interact.

Understanding nominal passive channel performance is only the start; achieving routine repeatability of these channels adds a layer of complexity that many designers may not be prepared to face. To meet the challenge, it is critical to work closely with a fabricator that not only understands the tolerances associated with the fabrication processes, but more importantly, understands how they affect the performance of the board.
TABLE 1. Channel Loss and Noise Summary

Channel loss Transmission lines Material loss
 Conductor loss

 Impedance mismatches PCB tolerance
 Connector tolerance
 Reflected noise Connector launch

Channel noise Crosstalk PCB transmission lines
 Connector architecture
 Connector launch

Channel loss LOSS POTENTIAL NOISE POTENTIAL

 -3.3dB
 -1.7dB
 -0.1dB
Channel noise -0.1dB

 -2dB to 30dB <-40dB
 -90dB
 -30dB
 -22dB+

Channel loss DESIGNER CONTROL

 Limited
 Limited
 Cost
Channel noise ?


REFERENCES

(1.) Tom Cohen, "Via Formation Fabrication Guidelines for Backdrilling," PCD&M, November 2003.

BIBLIOGRAPHY

John Mitchell and Bodhi Das, "A High Channel Density, Ultra High Bandwidth Reference Backplane Designed and Manufactured for 10 Gb/s NRZ Signaling," DesignCon Proceedings, February 2004.

MIKE OLTMANNS is technical marketing manager for Northrop Grumman's Interconnect Technologies division. He has a bachelor's in electrical engineering from the University of Illinois at Urbana-Champaign and an MBA from Northwestern University. He can be reached at 847-297-6183; m_oltmanns@comcast.net.
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Title Annotation:Design
Author:Oltmanns, Mike
Publication:Printed Circuit Design & Manufacture
Date:Jul 1, 2004
Words:1948
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