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Redefining memory test.

Memory device markets are more uncertain today than perhaps they have been in their entire history. In manufacturing, uncertainty can be addressed by equipment that can scale to needs and is flexible to adapt to changes in products. In the memory test business, uncertainty can take the form of changing pin-counts; test strategies such as wafer sort, known good die (KGD), and core final test; and even device technology including DRAM, flash, and multichip packages (MCPs).

A system that can scale to meet test needs as they change over the life of the system has value against the uncertainty. However, to be effective, the system must have a low cost of test (COT) in all conditions.

Flexibility with low COT is a challenge for the memory ATE industry. Low COT in all high-volume cases can be achieved through high parallelism. A test system with breakthrough parallelism--enough resources to test even DRAM with a single touchdown per 300-mm wafer--can have both flexibility and the required low COT.

Advantages of Increasing Test Parallelism

Even in uncertain markets, reduction of COT is a goal that device manufacturers pursue. One reliable way to reduce COT for high-volume production is to increase the parallelism of the tester. Due to efficiency of design, increasing test parallelism reduces the cost per pin of the tester. But even without the reduced cost per pin of the tester, significant COT advantages can be realized by using fewer higher throughput testers, resulting in fewer test cells.

Generally, the methods of increasing parallelism for a DRAM tester have differed from those for a flash tester. DRAM requires more pin electronics (PE) while flash testing uses more pattern generators. Wafer sort and final test applications each have unique issues that limit parallelism. Wafer sort parallelism currently is limited either by probe-card technology or wafer size. Final test parallelism generally is limited by handler technology. Handlers become limited by physical size and challenges to index and mechanically move/sort the devices.

By using fewer higher throughput testers to reduce the number of test cells, fewer probers/handlers are required on the test floor. The capital as well as the support and operating costs of the handler/probers are saved. Likewise, less floor space and fewer operators are required.

Added equipment may be required to match the tester parallelism, for example, a handler with more sites or a prober with a chuck to support the additional pressure from the probe contacts. However, despite the added equipment costs, the overall cost per throughput of the test cell is reduced.

Probe-card expense significantly increases with parallelism to the point where probe-card costs across the life of a test cell can exceed that of the tester. While this cost is offset by other savings in the case of long device runs, it might exceed the benefits in cases with a high mix of device types and probe card designs with low run volumes.

Challenges of Increasing Test Parallelism With PE

Testing more devices in parallel requires more resources to test the additional pins. Some resources can be shared, more so for DRAM test, less so for flash test.

Traditionally, additional PE resources are increased by either adding more pins, sharing the resource by connecting it to the same pin on multiple DUTs, or designing dedicated pins with reduced functionality. The most direct and the more expensive way to add parallelism is to add more PE with full functionality. This comes with several drawbacks: cost, power, cooling, space required, and lower reliability.

Cost is the first disadvantage. PE cost scales directly with parallelism. Additional tester pins require more power and more cooling. The parallelism of the tester can become limited not by the needs of the test cell, but by the power consumption of the PE.

Additionally, added power and associated cooling increase the physical space needed for the PE, preventing the drivers and comparators from being located near the device pins. The result is longer transmission lines, longer bus turnaround times, and greater capacitive loads the devices must drive.

While the tester drivers can be calibrated to drive longer lines, the signals returning from the DUT cannot, so an attenuated signal reaches the comparators. This potentially causes lost yield of devices that cannot drive the increased load although the devices would otherwise meet the specifications required for their intended application.

The scope plot in Figure 1 shows a 440-MHz signal seen 18 cm (larger) from the driver and 67 cm (smaller) from the driver. At 67 cm out, the signal is attenuated due to the additional capacitive load.


Adding more hardware also reduces system reliability. Mean time between failures (MTBF) decreases since there are more components each with a probability of failure. This must be addressed throughout the design and manufacturing process of the tester.

Considering cost, power requirements, and reliability, a tester utilizing only fully functional pins is inefficient for COT. The costs of these features are high, and much of this hardware is unused or underutilized for much of the test flow.

Increasing Parallelism Through Wired-OR

At the other extreme of the design options, PE resources can be shared directly through wired-OR. This is a very low-cost option to increase parallelism and can be done on the interface board. The tester hardware design needs little to no change, and wired-OR can be applied selectively for each device type to be tested.

Although the cost savings are great, so are the drawbacks to wired-OR configurations: lost functionality, lost performance, device interference, more complex software and usability, and added interface cost. Wired-OR is most effective for drive-only pins without the most critical timing specs.

Parallelism gains only are achieved for drive functionality with wired-OR. Parametric tests require a PMU, and device reads must be done serially. Signals passing through a wired-OR configuration are subject to attenuation and reflections caused by impedance mismatches where the lines split. This can result in lost yield.

In Figure 2, the split trace is ~5 inches and-80 [ohm]. Clear signal degradation is seen. For 1:4 sharing, attenuation is much greater because PCB trace impedance matching is not cost-effective.


While there are no additional costs in tester hardware, the additional load boards and probe cards required due to more complex signal routing and impedance matching will raise the cost. A single probe card can cost more than the entire tester over the life of the test cell. For that reason, these significant cost increases must be included in COT calculations.

As device pins are wired together, a shorted pin on one device can cause devices sharing its PE resource to fail as well, further reducing yield. At wafer sort with multiple touchdowns, pins that touch off-die can exacerbate this problem and must be addressed by adding cost or reducing parallelism. The use of relays or buffers addresses this problem but introduces more cost, reliability, and interface board layout issues.

In addition to the physical limitation of wired-OR pins, shared resources also complicate test-system test-program software. Data from serial PMU or device reads must be sorted and handled appropriately. The effect of this difficulty on COT is difficult to quantify accurately but significant.

Despite these drawbacks, wired-OR strategies commonly are used in memory device test. This is due to the low cost and the ability to use wired-OR selectively for only the device pins that are most tolerant to the drawbacks, such as input-only pins with loose timing requirements.

Dedicated PE Functionality

A compromise approach would provide pins with dedicated functionality, matching tester functionality to the test requirements and eliminating cost and functionality where not required. A tester that can be configured flexibly to have full I/O pins, drive-only pins (driver with timing and formatting, but no comparators), and DC-only pins (levels only, no timing, formatting, or compare) can be used effectively to lower COT for the target device.

This multiple pin-type approach is not a satisfactory solution due to the variety of devices to be tested. In uncertain market conditions where device designs are changing rapidly, test requirements can change significantly between device types and generations of the same device. The optimal pin configuration for one device might not be optimal for the next device design, requiring testers to be either dedicated for a particular device or over-configured to match a superset of the test needs.

A second issue with the multiple pin-type approach is the limitation it puts on interface designs. Added restrictions are problematic, especially at high parallelism where signal routing becomes challenging.

To handle multiple pin types, tester system software must be provided. Likewise, test programs must deal with the multiple pin types, sacrificing compatibility between some devices and test programs.

Active Matrix Approach

The patent-pending Active Matrix technology of the Verigy V6000 test platform redefines the PE available to the DUTs. This design provides high parallelism with the flexibility to meet a range of test needs at a lower cost than traditional PE while supporting better signal fidelity.

Three challenges were addressed by this design: the requisite that not all PE hardware is used for all tests, the need for a way to get all functionality to all pins, and the desire to provide the same or better signal fidelity to and from the device. The Active Matrix meets these challenges by adding a new matrix layer within the tester and redefining how the PE works.

To date, testers have used three types of PE, each with their own benefits and drawbacks, to address parallelism: standard I/O pins, wired-OR pins, and active fan-out designs (Figure 3).


I/O Pin

The standard, fully functional I/O pin provides good signal quality for good yield but lower throughput per hardware cost as compared to other options. Higher power requirements per pin can restrict tester design and limit proximity of the pin electronics to the DUT as well.


The wired-OR option provides high parallelism for high throughput per cost and low power requirements per pin but limited functionality and poor signal quality resulting in lower yield.

Active Fan-Out

The active fan-out PE design adds a buffer-per-device pin to the wired-OR design. This provides better drive signal quality and lower cost for additional parallelism. Reads still must be done in series with poor signal quality so this solution is most advantageous for input-only DUT pins.

The active fan-out has other advantages. Isolation between DUT pins and cleaner signals to the DUT result in significantly better yield than wired-OR at lower cost than standard I/O pins. And by decreasing the voltage range of the drivers such as no [V.sub.HH], power consumption is reduced, which enables these drivers to be more densely arranged nearer to the interface and therefore the DUT. When larger voltage swings are needed, the main driver can be used in multiple passes across DUT pins.

All of these solutions require tradeoffs in performance or cost. They create inflexibility in the system usage because the better solution of one device's test needs might be the worst solution for the next device's test needs. This inflexibility leads to dedicated test systems with short, useful life spans.

Active Matrix channels add a compare functionality to the active fan-out design. This meets the requirements on both input and I/O DUT pins to run main array functional tests at the highest parallelism. The reduced power requirements of the drivers and comparators allow them to be placed more densely and closer to the DUT, improving the signal quality delivered to the DUT and reducing the capacitive load the DUT must drive during functional tests.

The new matrix layer of the Active Matrix design is included in the test head. It provides the capability for the higher functionality PE hardware used in only a small portion of the test flow to be switched to device pins as needed. While all DUT pins are connected in parallel, multiple passes may be required to test all pins.

The result of the Active Matrix is better yield due to proximity of the PE and high parallelism including reads for functional tests. It also provides some functionality at a lower parallelism and eliminates the restrictions associated by multiple pin types. To evaluate this trade-off, parallelism must be revisited, taking into account the test requirements during the test flow.

Parallelism by Parts

With current PE designs, parallelism is examined for an entire test flow. Active Matrix technology breaks down the test flow by test functionality, similar to how PMUs for parametric tests have been implemented in memory test for many years: PMUs shared across pins, reducing the cost of the tester while increasing test time for parametric tests. As parametric tests typically are short, this trade-off can result in a lowered COT.

Parametric tests require a PMU and can account for an estimated 1% of overall test time for flash and 10% for DRAM. While a PMU per pin can decrease test time, the throughput increase is not as significant as the savings. This is an opportunity for tester design to save money and alleviate power restrictions by using fewer PMUs.

To measure AC parameters, a PMU is not required, but a driver, full comparator, and possibly window strobe capability are. Device interface tests measure the quality of output signals from the device. While these parameters are verified, the output stages of the DUT are tested.

Since the functionality of the main array is not being measured, there is no need to access each address of the main array multiple times as there is with functional tests. As device sizes increase, the number of cycles needed to make AC measurements, and therefore test time, does not increase proportionately.

Functional tests require the bulk of test time, typically about 90% for both DRAM and flash since the full memory array of the DUT must be accessed multiple times for each test. The PE hardware for a functional test includes a driver and a single comparator to verify that the DUT IOs drive the correct data. Consequently, increasing parallelism with PE to address these functional tests offers the greatest opportunity to reduce COT.

The Active Matrix provides selective high-parallelism where the most value is gained while meeting power restrictions within the tester. This trades off a large portion of the tester hardware cost for a small portion of test time, reducing the overall COT.

The design allows for an all I/O configuration for simpler interface design, saving interface cost. And since the PE can be located closer to the DUT, the DUT I/Os drive a channel with lower capacitive load than a traditional PE channel. This more closely matches the end use of the DUT and potentially results in higher yield.


To achieve COT advantages, tester hardware can be optimized to provide the highest parallelism for the greatest part of the test flow. By targeting the functional tests of the main array, PE channel cost and power consumption can be minimized while achieving high parallelism for the majority of test time for both flash and DRAM.

Having more functionality at lower parallelism in series with the high-parallelism hardware provides lowest COT for typical test flows. This high pin-count and improved performance translate to greater parallelism and lower COT for all memory device types.

About the Author

Scott West is a product manager at Verigy. He has 14 years of experience in the memory ATE industry including applications and marketing experience at Teradyne, Credence, and IMS as well as management consulting experience with Barris Lotterer. Mr. West received a B.S. in engineering from Harvey Mudd College and a master of engineering degree from Claremont Graduate School. Verigy, Memory Test Solutions, 10100 N. Tantau Ave., Cupertino, CA 95014, 503-804-2571, e-mail:

by Scott West, Verigy
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Title Annotation:IC ATE
Author:West, Scott
Publication:EE-Evaluation Engineering
Geographic Code:1USA
Date:Jan 1, 2009
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