Programmable single chip master/target PCI bridge solution.
This new device is ideal for applications that require the transfer of data between the PCI bus and high-throughput video compression/decompression, encryption/decryption, packet processing, DMA and other data processing sub-systems. Examples of such applications include: Edge routers that use multiple DMA engines for packet processing and block manipulation, T1/E1 channelizer cards that must transfer data from multiple HDLC channels to or from the PCI bus, and image processing applications in which a large FPGA or DSP may be used for video compression/decompression before sending the data to a hard drive or network.
On-chip FPGA Provides Short Design Cycle For Custom Interfaces--Historically designers of medium volume products who cannot afford the high NREs associated with masked ASICs have had two options for interfacing proprietary buses to the PCI bus: 1) a multi-chip discrete solution using an ASSP and FPGA; or 2) a stand-alone FPGA with a soft intellectual property (IP) core for the PCI controller. While the multi-chip discrete solution avoids the timing problems and verification issues associated with using soft IP, this approach requires additional board space and increases system power consumption. On the other hand, a single-chip FPGA-based solution requires months of extra design time to develop and debug the PCI interface and resolve timing problems. In addition, the PCI bus initialization process must frequently be slowed down to allow enough time for an SRAM-based FPGA to be loaded and enumerated. If bus enumeration takes place before the FPGA is loaded, the PCI controller will not be operable. In any standard PCI plug-in card, bus initialization cannot be slowed because it is controlled by the system BIOS. In these cases, SRAM-based FPGA loading latency introduces the very serious risk of card inoperability.
QuickLogic's QL5632 offers the reliability, short design cycle and instant-on benefits of a fully verified, hardwired ASSP PCI controller with the flexibility of an FPGA in a high throughput single-chip solution.
Instant-on Feature Supports BIOS-Controlled Bus Enumeration--QuickLogic's QL5632 programmable PCI bridge IC maintains its configuration even when the system power is off. Since there is no loading latency during system power-up, the device is always enumerated by the PCI bus. This feature makes the QL5632 ideal for plug-in cards in systems in which the BIOS controls bus enumeration.
QuickLogic's patented ViaLink FPGA configuration technology uses vias between the various metal layers for interconnect that provide 100% routability for the QL5632 FPGA fabric. ViaLink is a interconnect switch technology that supports field, programmability, high performance and low power consumption. Since there is no external configuration EEPROM, designs cannot be reverse engineered, which means they are secure from competition cloning or copying.
With the introduction of the QL5632, QuickLogic has six programmable PCI Bridge solutions, including master/target and target solutions for both 32-bit and 64-bit PCI buses with operating frequencies of 33, 66, and 75-MHz. FPGA densities range from 50K to 200K gates in a wide variety of packages.
In addition QuickLogic offers a variety of hot swappable PCI bridge ASSPs including 32-bit system master, bus master, bus target, and stand-alone target for 33 MHz and 50 MHz PCI busses, with internal bus speeds ranging from 33 MHz to 75 MHz.
Other Bridge Products--QuickLogic also offers a wide variety of ASSPs bridge products, including Gigabit Ethernet to PL3, Utopia to PL3, PL3 to PL3, Utopia to Utopia, TI DSP to PCI and CSIX to LVDS. Through its QuickASSP and QuickDR programs QuickLogic can provide "custom" ASSPs to meet virtually any bridging application.
QuickLogic's QL5632 is available now in 280-pin PBGA and 208-pin PQTP packages and is priced at $21 in quantities of 25,000 units.
QuickLogic's ESP families offer standard product time-to-market and economics coupled with user customizable logic--on the same piece of silicon. The performance, power and cost advantages provided by these innovative devices and QuickLogic's ViaLink based logic architecture, make these integrated circuits ideal for high-speed, low-power applications such as data and telecom systems, instrumentation and test systems. QuickLogic ESP families include QuickMIPS, QuickPCI, QuickRAM, QuickDSP, QuickFC and QuickSD.
QuickLogic Corporation (Nasdaq:QUIK) began developing the Embedded Standard Product (ESP) architecture in 1998, an innovation that delivers the guaranteed performance and lower cost of standard semiconductor products and the flexibility and time-to-market benefits of programmable logic. QuickLogic's ViaLink metal-to-metal interconnect technology offers high performance and is the foundation of the company's ESP families as well as our core FPGA products.
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|Title Annotation:||QuickLogic QL5632|
|Publication:||EDP Weekly's IT Monitor|
|Date:||Nov 25, 2002|
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