Predicting reliability of double-sided area array assemblies.
Determining reliability by simulation is much faster and more cost effective than laboratory testing, but current finite element modeling techniques are only proven for single-sided assemblies. By physically testing a representative selection of assemblies and comparing the results with predictions generated using known models, assessing the applicability of current modeling techniques to double-sided assemblies is possible. If an acceptable correlation can be found, designers will be able to use existing finite dement models to gain accurate reliability predictions and thereby optimize the layout of future double-sided boards.
The effects of components placed on both sides of a test board were studied. The components included CSPs, BGAs, QFPs and chip capacitors. Various configurations of double-sided assemblies were studied. These included symmetrically double-sided assemblies (mirror image assemblies), 50% overlap assemblies and assemblies with an area array component on one side and chip capacitors of various sizes on the other side.
Cycles-to-failure were documented for all assemblies, and the data were used to calculate the characteristic life. In addition, moire interferometry was used to study the displacement distribution in the solder joints at specific locations in the packages.
Each of these assemblies was then simulated using existing finite element models to predict displacement over time due to thermal cycling. These predictions were then compared with displacements measured directly from the moire data to establish a correlation between the behavior of each simulation and its corresponding physical sample. Having proved an acceptable correlation between measured and predicted displacement, the team estimated the fatigue life of solder joints in each simulated assembly by applying Darveaux's crack propagation formula, from which an estimate of the overall package reliability was obtained. The estimate for each simulated assembly was then compared with the empirical data, and a correlation was established by inspection.
Components and Test Configurations
Seven surface-mount devices were utilized in this study:
* 64 I/O CSP with 0.8 mm bump-to-bump pitch
* 256 I/O BGA with 1.27 mm bump-to-bump pitch
* 208 I/O QFP with 0.5 mm bump-to-bump pitch
* 0402 surface-mount capacitor
* 0603 surface-mount capacitor
* 0805 surface-mount capacitor
* 1206 surface-mount capacitor.
Eight basic test configurations were assembled on a daisy-chained 0.062 in. thick PCB. The CSP family assemblies used a 0.93 in. x 0.93 in. PCB coupon, while the BGA and QFP assemblies used a 1.73 in. x 1.73 in. PCB coupon.
The eight main configurations were:
* single-sided CSP using 0.012 in. diameter non-solder masked defined (NSMD) PCB pads
* double-sided mirror image CSP using 0.012 in. diameter NSMD PCB pads
* double-sided 50% offset CSP using 0.012 in. diameter NSMD PCB pads
* front-side CSP with 0.012 in. diameter NSMD PCB pads and backside capacitors. The backside capacitor array consisted of 31 devices. Four different capacitor configurations that were used were 0402, 0603, 0805 and 1206. Note that capacitor performance was not monitored during reliability testing.
* single-sided BGA assembled using 0.020 in., 0.022 in. or 0.024 in. NSMD pads
* double-sided mirror image BGA assembled with 0.020 in. or 0.022 in. NSMD pads
* front-side BGA assembled using 0.022 in. or 0.024 in. NSMD pads with backside QFP assembled to 0.012 in. x 0.060 in. rectangular NSMD pads
* single-sided QFP assembled with 0.012 in. x 0.060 in. rectangular NSMD pads.
Accelerated Thermal Cycle
The assemblies were exposed to a 30-minute, 0[degrees]C to 100[degrees]C air-to-air thermal cycle (AATC). The thermal cycle consisted of five-minute dwells at the temperature extremes and 10-minute transition periods (+/-10[degrees] C/min.). Temperature variation within the thermal chamber conformed to IPC-9701.
The test assemblies were attached to an event detection system (EDS) while inside the thermal cycling chamber. The EDS continuously monitored the electrical integrity of the test assembly and recorded electrical events or momentary resistance changes greater than 300[ohm] for a minimum duration of 200ns. Failure was defined per IPC-9701 that requires the first event be confirmed by nine additional events within 10% of the cyclic lifetime.
The following assembly combinations were evaluated by AATC:
* single-sided CSP
* double-sided mirror image CSP
* double-sided 50% offset CSP
* CSP with backside capacitors
* single-sided BGA
* double-sided mirror image BGA
* BGA with backside QFP
* single-sided QFP
Table 1 summarizes the reliability measurements of the assemblies. This table shows that:
* The single-sided CSP had the highest reliability among all CSP samples.
* The addition of progressively larger backside capacitors decreased the reliability of the CSP.
* The double-sided mirror image CSP was the least reliable CSP assembly.
* The double-sided 50% offset CSP assembly performed 26% better than the mirror image assembly but still performed considerably lower than any other CSP assembly.
* Single-sided BGA reliability was comparable to the BGA reliability of BGA/QFP assemblies.
* Double-sided mirror image BGA assemblies were 3X less reliable than the single-sided BGA assemblies.
* Neither the single-sided QFPs nor the QFPs used in BGA/QFP assemblies failed.
* A backside QFP did not adversely affect the reliability of a topside BGA.
* Increasing PCB pad diameter while keeping the solder volume constant resulted in decreased BGA reliability.
Moire interferometry is an optical technique for measuring displacement in a specimen. The results of a moire analysis are full-field in-plane displacements in the form of a fringe pattern viewed on the surface of the specimen.
The assemblies were cross-sectioned to expose a row of solder joints for moire displacement analysis. After setup and calibration, the fringe-shifting technique was used to obtain a series of interference pattern images. These were post-processed to determine the fringe patterns indicating the desired contours of displacement. The moire pattern for the double-sided BGA assembly is shown in Figure 1.
[FIGURE 1 OMITTED]
Finite Element Modeling
The finite element analysis (FEA) software package was used to simulate joint behavior in the single-sided and mirror image CSP and BGA assemblies, as well as the 50% offset CSP assembly. The finite element model for the 50% offset CSP assembly is shown in Figure 2.
[FIGURE 2 OMITTED]
The software features well-developed viscoplastic analysis capabilities that allow the inelastic properties of solder, namely time-dependent creep and time-independent plasticity, to be modeled very accurately. These models have been successfully applied to calculate the viscoplastic strain energy density at solder interconnects in many types of electronic packages and assemblies. These include CSPs, multiple BGAs, power modules, micro-miniature electronic packages and multi-chip silicon based system-in-package assemblies.
By simulating identical loading and boundary conditions as those applied to gather the moire images from the laboratory samples, predicting horizontal displacement in the finite element model of each assembly was possible. For the single-sided BGA assembly, the predicted horizontal displacement in the worst-case solder joint (die shadow) was 114 [micro]in., while the measured displacement via moire was 98.5 [micro]in. This measurement represents approximately a 15% difference, indicating very good correlation.
In the double-sided BGA assembly case, the predicted displacements were within approximately 25% of the measurement. Again, this good correlation between the model and measurement inspires a certain level of confidence in the models. Consequently, in the next section, the models were used to predict the fatigue life of the single- and double-sided assemblies.
Finite Element Reliability Prediction
In addition to solder constitutive modeling, an energy-based metric for predicting crack initiation and growth in solder joints has also been developed. Much of this work is attributed to Darveaux, whose nonlinear material testing on actual soldered joints has yielded crack growth data that can be combined with the viscoplastic strain energy density calculated to predict the number of cycles to initiate a crack and the number of cycles for the crack to propagate across the diameter of the solder joint.
Darveaux's work has resolved the time to failure for a given solder joint into two components: the time-to-formation of the first crack in the solder joint and the subsequent rate of crack growth per thermal cycle. This formula is expressed as follows:
[N.sub.a] = [N.sub.o] + da/dN
where [N.sub.o] is the number of cycles to crack initiation and da/dN is the crack growth rate per cycle N.
Darveaux also found that:
[N.sub.o] = A[Delta][W.sup.B.sub.ave]
da/dN = C[Delta][W.sup.d.sub.ave]
where A, B, C, D are constants that are dependent on material and element size and [Delta][W.sub.ave] is the volume averaged viscoplastic strain energy density increment.
By analyzing actual solder joints, Darveaux has derived a table of constants for solder joints of various dimensions. Our team was thus able to select constants that were appropriate to the sizes of solder joints that were subjected to AATC to make direct comparisons between the simulated and experimental assemblies. The values selected from Darveaux's table are shown in Table 2.
From this, Darveaux's crack propagation method was used to determine the life of the solder joints. The reliability, or number of survivors, was then calculated using the two-parameter Weibull distribution:
R = [e.sup.-(N/N[Alpha])[.sup.[Beta]]
where R is the reliability and N is the number of cycles to achieve that reliability.
The two parameters are [N.sub.[Alpha]] (the characteristic life) and [Beta] (the shape parameter or Weibull slope). For a series of joints connected electrically, the overall reliability of all the joints is given by the product of the reliability of each joint in the series. With the characteristic of each joint computed from the finite element calculations using the crack growth rate approach, the cycles-to-failure versus reliability relationship can then be generated for any assumed shape parameter. A fixed Weibull slope of 4.0 was assumed in all models.
Results from the AATC finite element simulations for the single-sided and mirror image BGA and CSP assemblies, as well as for the 50% offset CSP, are presented in Table 3 with the corresponding results from experimental analysis.
For each joint, the predicted reliability was in very good agreement with measurements. The finite element models were also successful at capturing the subtle trend of decreasing reliability with increasing pad size, as was observed in the measurements. Note that the predicted reliability for the mirror image BGA was very conservative, yet it was still within the [+ or -]2X expected range of the measured values. These results indicate that the Darveaux crack propagation methodology can be successfully extended to finite element reliability modeling of double-sided assemblies.
Physical samples and finite element models of various configurations of double-sided assemblies have been analyzed. The reliability figures achieved by finite element modeling have been seen to correlate very closely to empirical results observed in our laboratory, with all predictions falling within the range expected for Darveaux's method. As building test assemblies and running reliability assessments is both expensive and time consuming, using existing finite element models is an accurate and cost-effective alternative when investigating the impact of double-sided components on the assembly reliability.
ABLE 1: Measured cycles-to-failure. Assembly Description Cycles-to-Failure ([N.sub.63]) PCB Coupon Dimensions 1.73" x 1.73" 0.93" x 0.93" CSP -- 6,140 CSP with 0402 -- 5,837 CSP with 0603 -- 5,369 CSP with 0805 -- 5,146 CSP with 1206 -- 5,069 CSP and 50% Offset CSP -- 3,026 Mirror Image CSP -- 2,396 BGA (0.020" Pad) 8,284 -- BGA (0.022" Pad) 7,897 -- BGA (0.024" Pad) 7,736 -- Mirror Image BGA (0.020" Pad) 2,890 -- Mirror Image BGA (0.022" Pad) 2,719 -- QFP >10,000 -- BGA (0.022" Pad) with QFP 8,161 (BGA) -- BGA (0.024" Pad) with QFP 8,010 (BGA) -- TABLE 2: Suggested constants for use in predicting 62Sn36Pb2Ag solder fatigue. Thickness Along Interface [0.001"] A B C D 0.5 71,000 -1.62 2.76 1.05 1.0 56,300 -1.62 3.34 1.04 1.5 48,300 -1.64 3.80 1.04 TABLE 3: Summary of assembly reliability results. Assembly Reliability (cycles) Measured Predicted Single-Sided BGA (20 mil pad) 8,284 8,153 Single-Sided BGA (22 mil pad) 7,897 7,991 Single-Sided BGA (24 mil pad) 7,736 7,814 Mirror Image BGA 1,576 2,890 Single-Sided CSP 7,611 6,140 Mirror Image CSP 3,174 2,300 50% Offset CSP 3,026 3,000
This study was carried out by Anthony Primavera, Ph.D., and Mike Meilunas of Universal Instruments Corp. and James M. Pitarresi, Ph.D., Shiva Kalyan Mandepudi and Satish Parupalli of Binghamton University, State University of New York.
Anthony Primavera, Ph.D., is a former process research engineer with Universal Instruments Corp., Binghamton, NY; (607) 779-7522; email: email@example.com.
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|Title Annotation:||Component Placement|
|Date:||Oct 1, 2003|
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