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Power contours for microwave HBTs.

A simple method for calculating microwave power contours on the output impedance plane for heterojunction bipolar transistors (HBT) is presented. These contours are used to quantify power and gain tradeoffs and are also useful in design of impedance matching circuits for large signal HBT operation. The relationship of output impedance matching to amplifier dynamic range and conventional load-pull measurements is discussed.

Introduction

Designs for AIGaAs/GaAs heterojunction bipolar transistor monolithic integrated circuits rely on measured S-parameters to model the active devices used. From the S-parameters, it is possible to calculate small signal gain circles on the output impedance Smith Chart using CAD programs, such as SuperCompact|R~ or Touchstone|R~.

S-parameters can be applicable in the large signal case to the extent that nonlinearities and saturation effects are not important. However, S-parameters alone are not sufficient to predict high power operation. It would be useful to associate points on the gain circles with power and efficiency performance of the transistor. This paper shows how DC measurements can be used to provide a more complete picture of device performance. In this analysis, power contours are calculated for HBTs with a method|1~ used for field effect transistors, which provides a determination of the load required for optimum power performance, as well as a prediction of that performance in the class A regime.

The HBT Model

To calculate the power contours of a common emitter HBT, the DC current-voltage (I-V) characteristics of the transistor, shown in Figure 1, are measured. The DC saturation resistance |R.sub.s~ is shown in relation to several important voltages and currents. The saturation resistance results primarily from the need for a finite collector voltage to reverse bias the collector-base junction when the base emitter junction is forward biased. Although |R.sub.s~ may include a small contribution from parasitic emitter and collector resistances, it is called a resistance.

The voltages and currents on the I-V plane are measured at DC. For the RF case, terminal voltages and currents must be interpreted with the aid of the equivalent circuit, shown in Figure 2a. This T model has been widely used to fit measured S-parameters over a frequency range up to 26 GHz. Typical values of the equivalent circuit elements for an AIGaAs/GaAs HBT with a total emitter area of 40 ||mu~m.sup.2~ are listed in Table 1. Such devices operated in class AB mode have demonstrated high power CW performance at 10 GHz with 0.8 W output power at 6.4 dB gain and 47 percent power-added efficiency. In the pulsed mode, peak power higher than CW levels can be obtained. For example, with pulse lengths of 300 ns and 33 percent duty cycle, the transistors give 1.8 W of peak power with 4.7 dB gain and 35 percent power-added efficiency.

At low frequency, where the DC measurements accurately describe the transistor response at its external terminals, the output circuit may be modeled for small |R.sub.e~ and small |R.sub.ee~, as shown in Figure 2b, which also defines a reference plane for the DC current and voltage. The HBT parasitic elements are modeled as resistors, and the active portion of the device is represented by the current generator. Maximum power is achieved by the load line, corresponding to a resistance |R.sub.o~ at this reference plane, where |R.sub.o~ = (B|V.sub.ceo~ -|V.sub.DC)/|I.sub.DC~. The 400 ||mu~m.sup.2~ HBTs have a value of 55 omega. The generator sees essentially the same load resistance if the simplifying assumption is made that the parasitic series resistances |R.sub.e~, |R.sub.ee~ and |R.sub.ce~ are small compared to |R.sub.o~, and that |R.sub.bc~ is as large as the Table 1 values.

In the low frequency case, it is assumed that the HBT behaves in a linear fashion until the signal becomes large enough to induce clipping of the output waveforms due to voltage or current swings beyond the boundaries of the I-V curves. For voltage, the high boundary is the RF breakdown voltage and the low boundary is the saturation line (|R.sub.s~). For current, the boundary is the |I.sub.c~ = 0 axis. Drive levels to these boundaries are maintained throughout the calculations. Accordingly, the power contours to be calculated are not the usual load-pull contours most often obtained by measurement,|2~ but rather full-drive contours more useful for amplifier design.

The difference between these contour types is significant. By definition, a load-pull contour is the locus of points on the Smith Chart describing the external load such that the output power is constant with fixed input power and fixed generator impedance. For some values of output impedance, the fixed input power may result in clipping of either the output current or voltage waveform.|3~ If this occurs, the transistor is overdriven and output distortion results. At other values of output impedance, where the transistor is underdriven, high power and efficiency with no output distortion and undiminished gain can be obtained by increasing the RF input power. The threshold with increasing RF input power for overdrive is defined as fully driven class A operation. For amplifier design purposes, it is helpful to have knowledge of the output power contours at full drive so that the trade-off between maximum class A power and gain can be determined. Thus, for each load impedance, the RF drive and generator impedance would be considered adjustable to provide the maximum class A output power. From knowledge of the power gain and full drive class A power associated with the load impedance, the required input power can be determined. The analysis can be further extended to give information about the dynamic range of the transistors.

For the low frequency case, the current and voltage at the DC reference plane is significant. Indeed, it can be shown|3~ that when the current and voltage have the correct ratio, that is, (|V.sub.c/I.sub.c) = -|R.sub.o~, they move along a straight line trajectory during the RF cycle so that DC power dissipation in the transistor is minimal compared to all other straight line trajectories passing through the bias point (|V.sub.DC~, |I.sub.DC) and extending to the boundaries of the I-V characteristics. Hence, when (|V.sub.L~/|I.sub.L~) = |R.sub.o~, power output is maximized compared to all other possible resistive loads.

At high frequencies, parasitic reactances must be taken into account. In this case, it is useful to introduce an internal reference plane directly at the terminals of the current generator. Kirchhoff's equations may be solved for the equivalent circuit of Figure 2a to give the transformation between the effective load impedance at the internal reference plane |Z.sub.r~ and the impedance at external reference plane |Z.sub.L~. The result is

|Mathematical Expression Omitted~

where

|Z.sub.o~ = 1/j|omega~|C.sub.o~ |Z.sub.bc~ = (j|omega~|C.sub.bc~ +1/|R.sub.bc~)|sup.-1~ |Z.sub.e~ = total impedance in the emitter branch

The subscripts L and r are used for circuit parameters at the external load and the internal reference plane, respectively.

|Z.sub.L~ has a simple approximation when expressed in terms of admittances

|Y.sub.L~ = 1/|Z.sub.L~ and |Y.sub.r~ = 1/|Z.sub.r~

|Mathematical Expression Omitted~ (2)

where the series emitter and collector parasitic resistances are assumed small compared with the load resistance. The primary effect of high frequency operation is the insertion of shunt capacitance in parallel with the load. Any output impedance matching method that maximizes class A power must transform the external load impedance to an effective value |R.sub.o~ at the internal reference plane.

Equations 1 and 2 are independent of input generator impedance. This is a consequence of having a controlled source in the equivalent circuit and is the reason |Z.sub.r~ is referred to as an effective impedance. Equation 2 indicates that the external load must contain a shunt inductance to resonate the transistor feedback capacitance. The transformation is easily visualized on a Smith Chart, where the optimum DC load only needs to be moved along a line of constant admittance to give the high frequency optimum impedance match point.

A detrimental effect of the shunt inductance is reduction of the real part of the optimum external load impedance that requires higher RF currents to maintain a given power. Indeed, the peak RF current through the load can exceed the DC bias current. The additional current is supplied by charge storage in the parasitic capacitance associated with the transistor. Higher current makes parasitic collector and emitter resistance more significant absorbers of useful power. Components of these resistances that do not scale with transistor active area can ultimately limit the size of HBTs for high power.

Power Contours

In amplifier operation, |V.sub.DC~ is chosen to maximize the RF voltage swing that is assumed to be limited at the high end by the base-emitter breakdown voltage B|V.sub.ceo~, and at the low end by the 1/|R.sub.s~ line. In a practical case, the voltage limit will be determined by either the high or low limit depending on the value of |V.sub.DC~. If the effect of small parasitic resistances is again ignored, the dissipated power will be the same at the internal and external reference planes.

Case 1--High |V.sub.DC~

The high |V.sub.DC~ case, shown in Figure 3a, is considered first, where |V.sub.DC~ is high enough such that B|V.sub.ceo~ limits the voltage swing. For fixed bias, the associated full drive power is obtained with |R.sub.r~ = |R.sub.o~ = (B|V.sub.ceo~ - |V.sub.DC~)/|I.sub.DC~. The associated power is

|Mathematical Expression Omitted~ (3)

where

|I.sub.r~ = |I.sub.DC~

If the effective load resistance Rr is increased or decreased with the bias current, and the voltage is held constant, the resulting RF voltage and current amplitudes are limited by |V.sub.c~ = B|V.sub.ceo~ or |I.sub.c~ = 0 depending on whether |R.sub.r~ |is greater than~ |R.sub.o~ or |R.sub.r~ |is less than~ |R.sub.o~, respectively. To remain fully driven, the input power must be adjusted for each value of |R.sub.r~.

More generally, |Z.sub.r~ = |R.sub.r~ + j|X.sub.r~ so that the effective load contains a reactive part. The transistor RF current |I.sub.r~ and RF voltage |V.sub.r~ across the current generator will then have a phase difference other than 180|degrees~. The current-voltage trajectory will be an ellipse superimposed on the I-V contours.|1~ At the internal reference plane and for |R.sub.r~ |is less than~ |R.sub.o~, Equation 3 is generalized to

|Mathematical Expression Omitted~ (4)

independent of |X.sub.r~. Therefore, a constant power contour at the internal reference planes will be a portion of a resistance arc on the Smith Chart. There will be a maximum reactance magnitude consistent with the boundary conditions of |V.sub.ce~ |is less than~ B|V.sub.ceo~ that defines the end points of the arc.

The open shape of the I-V trajectory at these impedance end points is identical with that corresponding to saturated voltage operation with effective output admittance of |Y.sub.r~ = |G.sub.r~ + j|B.sub.r~ = 1/|Z.sub.r~. For |R.sub.r~ |is greater than~ |R.sub.o~, power is independent of |B.sub.r~ and given by

|Mathematical Expression Omitted~ (5)

where

|V.sub.r~ = B|V.sub.ceo~-|V.sub.DC~

Thus, the remainder of the power contour at the internal reference plane is formed by the constant conductance arc on the Smith Chart. Along this arc, |R.sub.r~ |is greater than~ |R.sub.o~. The boundary conditions for saturation relate to the region on the I-V plane. When |R.sub.r~ = |R.sub.o~, no load reactance is permitted without violating the saturation boundary conditions.

The described power contours were derived for the internal reference plane. To refer them to the external load, a shunt inductance must be added. On the Smith Chart, each point on the internal referenced plane power contour must be moved counterclockwise along a line of constant conductance.

Case 2--Low |V.sub.DC~

The case where B|V.sub.ceo~ provides an RF voltage limit has been considered. The low voltage case where |V.sub.DC~ is sufficiently small compared with B|V.sub.ceo~ such that the RF voltage swing is limited by intersection of the |R.sub.o~ load line with the saturation resistance line, as shown in Figure 3b, is considered. The low |V.sub.DC~, high |I.sub.DC~ case where |I.sub.DC~ is so high that the current cannot swing down to |I.sub.r~ = 0, resulting in low efficiency operation is ignored because of its insignificance.

Now at full drive, |R.sub.o~ = |(|V.sub.DC~ --|V.sub.o~)/|I.sub.DC~~ -2|R.sub.s~ and the power output for |R.sub.r~ |is less than or equal to~ |R.sub.o~ will still be given by Equation 4, but increased RF voltage swing will be possible for |R.sub.r~ |is greater than~ |R.sub.o~. It can be shown|3~ that for fully driven class A operation with |R.sub.r~ |is greater than~ |R.sub.o~, and with the I-V trajectory intersecting the |R.sub.s~-line boundary, the RF voltage amplitude is given by

|Mathematical Expression Omitted~

The power output is still given by Equation 5 or

|Mathematical Expression Omitted~

where

|Mathematical Expression Omitted~ |V.sub.o~ = HBT offset voltage

The procedure for determining the constant resistance portion of the power contours for low |V.sub.DC~ is similar to that described for the case of higher |V.sub.DC~. However, for the remaining portion, Equation 7 is solved to give |G.sub.r~

|Mathematical Expression Omitted~

where

|Mathematical Expression Omitted~

The quantity |xi~ is often small enough to be neglected, making it a curve of constant conductance.

The discussed concepts can be applied in a practical approach to design an HBT power amplifier. The curves of Figure 4 are used to choose bias conditions. |R.sub.o~ is plotted for various output powers using Equation 3. Superimposed on this set of curves is a second set from the equation |R.sub.o~ = |V.sub.r~/|I.sub.DC~. Thus, to determine the minimum RF voltage and value of |R.sub.o~ necessary for any given saturated class A power, the desired power curve and the voltage curve intersection at the desired current are selected. The minimum |V.sub.DC~ is then obtained by solving Equation 6, assuring that |V.sub.DC~ + |V.sub.RF~ |is less than~ B|V.sub.ceo~. At this bias point, S-parameters are measured and the equivalent circuit elements |C.sub.o~ and |C.sub.bc~ are determined by fitting the data. The required external power impedance match point |Z.sub.max~ is calculated from Equation 2 to be

|Mathematical Expression Omitted~

To generate the complete set of full drive class A power contours at the external reference plane, the constant resistance and conductance circles at the internal reference planes can be transformed to the external plane using Equation 2 in a similar manner.

Application to an X-Band HBT

The described method is applied to a high power HBT, which was comprised of 10 cells, each with an emitter finger size of 3 x 20 ||mu~m.sup.2~. To make small signal measurements at a bias point where heating would not be excessive, bias conditions |V.sub.DC~ = 4 V and |I.sub.DC~ = 100 mA were chosen. From DC measurement, |R.sub.s~ = 2.68 omega |V.sub.o~ = 0.12 V and B|V.sub.ceo~ = 12 V. According to Equations 3 and 8, the maximum class A power at this bias is 167 mW with |R.sub.o~ = 33.4 omega. This corresponds to the measured point in Figure 4 with |V.sub.RF~ = 3.3 V, resulting in an RF voltage swing limited by |R.sub.s~ rather than B|V.sub.ceo~.

For the bias values and operating parameters chosen, the power contours shown in Figure 5 were calculated at the output plane for 10 GHz by the outlined procedures. Superimposed on the contours are the transistor gain circles at the external load obtained from S-parameter measurements on the same device. The equivalent circuit elements in Table 1 apply to this transistor. In calculating the gain circles, it is assumed that the input of the transistor is conjugately matched at every load impedance. The predicted maximum available gain is 10.9 dB with an associated power of 21 dBm. Maximum class A power of 22.2 dBm is predicted with slightly less gain. From the bias conditions of |I.sub.DC~ = 100 mA, |V.sub.DC~ = 4 V, an expected collector efficiency of 42 percent and a power-added efficiency of 38 percent at the maximum power point, are calculated. The collector efficiency is less than the maximum theoretical value of 50 percent for class A operation. This is due to the finite offset voltage and |R.sub.s~ of the transistor.|3~ Higher class A efficiencies can be obtained by operating devices at higher voltages and using transistors with lower values of |R.sub.s~ and offset voltage. The maximum gain and power point are close in the example, which will not always be the case. Displacement of these points can lead to reduced gain at maximum class A power.

To check the predictions of the analysis, load pull measurements on the transistor using computer controlled external tuners were conducted. Table 2 lists the measured maximum power points at various drive levels with the generator impedance held fixed at 2.1-j6.5 omega, the small signal conjugate match for the transistor. The HBT is nearly unilateral, so that variation of load impedance does not greatly affect the device input impedance. The calculated full drive, maximum power point is close to the maximum power point measured. Beyond 20.8 dBm, the sharp change in reactance suggests (within experimental error) power saturation.

Figure 5 offers insight into the relationship between input RF power level and overdrive at the transistor output terminals. This relationship is useful for selecting loads for maximum dynamic range. The posed question is what values of external load impedances can be presented to the HBT such that at a given input power, the collector voltage and the current waveforms will not be clipped by excursions outside the boundaries of the DC current-voltage curves. To produce undistorted output, a designer would select a load in an underdriven region of the external load Smith Chart. Knowledge of the boundaries on this region would be useful since there will be gain and efficiency trade-off considerations.

A technique for calculating the boundaries utilizes the power and gain contours of Figure 5. From these contours, contours of constant input power at full class A drive can be constructed. It is assumed that an input power of 10 dBm is provided and the load impedance is moved along the 10 dB gain circle to a point on the 20 dBm power contour. For this load, the transistor is fully driven. If the point is moved further on the 10 dB gain circle to within the 20 dBm power contour, higher full drive power is possible and the device is underdriven at 10 dBm input. Outside the 20 dBm power contour and on the 10 dB gain circle, the device is overdriven. By examining each gain and power contour for the condition |P.sub.RF~/gain = 10 dBm, a distortion boundary for 10 dBm input can be constructed, as shown in Figure 6. For any output load impedance inside the boundary, the transistor would be underdriven. For load impedances outside the boundary, the transistor would be overdriven. At very low output power level, the underdrive region expands to include most of the chart. As the power increases, the underdriven region shrinks to a point. This point is the output impedance required for maximum dynamic range of the amplifier. For this load impedance, the amplifier could tolerate the largest input power without clipping of the output waveform. This information would be useful to designers seeking tolerances for distortion-free HBT amplifier designs. The device parameters affecting the size and shape of the boundary are of interest to device designers.

The dynamic range analysis helps to interpret conventional loadpull measurements where the input power is held fixed as the output impedance is varied. For underdriven regions of the Smith Chart, the power contours should nearly coincide with the gain circles calculated from the S-parameters. The contours may depart from the small signal gain circles in the overdriven region of the chart.

Conclusion

Calculated power output contours can be used with S-parameter measurements to predict power and gain trade-offs in HBTs for a restricted class of operating conditions. A practical HBT amplifier design approach based on the calculations has been discussed. Measurements show reasonable agreement with predictions of power and associated gain. The model can be used to determine load impedance distortion boundaries to optimize the dynamic range of the HBT amplifier design.

Acknowledgment

The authors would like to thank R. Wohlert and M. Niedzwiecki for providing data for this work.

References

1. S.C. Cripps, "A Theory for the Predictions of GaAs FET Load-Pull Power Contours," IEEE MTT-S Symposium Digest, 1983, pp. 221-223.

2. D.A. Teeter, et. al., "Large Signal Characterization and Numerical Modeling of the GaAs/AIGaAs HBT," IEEE MTT-S Symposium Digest, 1991, pp. 651-654.

3. M.G. Adlerstein and M.P. Zaitlin, "Cutoff Operation of Heterojunction Bipolar Transistors," Microwave Journal, Vol. 34, No. 9, September 1991.

Michael G. Adlerstein received his BS degree in mathematics and his MS degree in physics simultaneously in 1966 from the Polytechnic Institute. He received his PhD degree and a second masters in 1971 from Harvard University. During a portion of his doctoral work, he was a visiting scientist at Massachusetts Institute of Technology, Francis Bitter National Magnet Laboratory. Since joining Raytheon Company, Research Division in 1971, Adlerstein has worked in the field of microwave and mm-wave, semiconductor device research. In 1987, he was appointed consulting scientist. Adlerstein has been associate editor for microwave devices of the IEEE Transactions on Electronic Devices (1981-1983) and is publication chairman of the Cornell University High Speed Electron Device Conference Committee. He is a life member of the American Physical Society, Sigma Xi, Sigma Pi Sigma and Pi Mu Epsilon. He is a senior member of the IEEE.

Mark P. Zaitlin received his AB degree in physics from the University of California, Berkeley in 1971 and his PhD in solidstate physics from the University of Illinois, Urbana in 1975. From 1975 to 1977, he did research as a post-doctoral fellow at the Ames Laboratory at Iowa State University. In 1977, he joined the physics faculty at Dartmouth College, where his research activities involved the study of superconducting properties of composite materials. Since 1983, he has been with the Research Division of Raytheon Company, where he has been working in the GaAs semiconductor group. His work has focused on advanced devices and he directed the development of the first quarter |mu~m gate length MBE MESFETs, HEMTs, and pseudomorphic HEMTs. Currently, he is fabricating and modeling HBTs for microwave power applications.
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Title Annotation:Technical Feature; heterojunction bipolar transistors
Author:Adlerstein, Michael G.; Zaitlin, Mark P.
Publication:Microwave Journal
Date:Mar 1, 1993
Words:3941
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