Power analysis by combining the modules PASTA using DGMOSFET.
Binary addition is one of the most important processes that a processor performs. Most of the adders have been designed using synchronous circuits although there is a strong interest in clock less/ asynchronous processors/circuits. Asynchronous circuits are those which do not consider any quantization of time. Therefore, they provide a great potential for logic design as they are free from several problems from clocked (synchronous) circuits. In general, logic flow in asynchronous circuits is maintained by a request-acknowledgment handshaking Protocol signals to establish a pipeline in the absence of clocks. Explicit handshaking blocks are micro elements, such as bit adders, are exclusive. Therefore, it is implicitly and effectively achieved using dual rail carry propagation in adders. A valid dual-rail carry output also affords an acknowledgment signal from a single-bit adder block. Thus, asynchronous adders are similar either full dual-rail encoding of all signals (more formally using null convention logic that uses symbolically correct logic in its place of Boolean logic) or pipelined operation using single-rail data encoding and dual-rail carry illustration for acknowledgment signals. While these constructs add stoutness to circuit designs and they also introduce major overhead to the average case performance on asynchronous adders add benefits. Therefore efficient substitute approach that can address these problem presents an asynchronous parallel self-timed adder (PASTA) using the algorithm originally proposed. The design of PASTA using dual gate MOSFET is fixed and uses half-adders (HAs) along with multiplexers requiring least interconnections. Thus, it is appropriate for implementation VLSI circuits. The design works in a parallel manner which is single as it employs feedback through XOR logic gates to constitute a single-rail cyclic asynchronous sequential adder. Cyclic circuits can be more effective on resource than their acyclic counterparts. In other way, wave pipelining (or maximal rate pipelining) is a technique that can apply pipelined inputs before the balance of outputs. The suggested circuit manages automatic single-rail pipelining of the carry inputs which is detached by propagation and inertial delays of the gates in the circuit path. Thus a single rail wave-pipelined method is effective and quite different from conventional pipelined adders using dual rail encoding to implicitly symbolize the pipelining of carry signals independent carry chain blocks.
Parallel adders are combinatorial design which is not clocked, does not have any memory and feedback circuit elements for adding every bit position of the operands in the same time. Fig 1 shows the parallel adder thus it demanding number of bit-adders which consists of (full adders + 1 half adder) equal to the number of bits to be added.
Self timed circuits:
An asynchronous circuits are also called self-timed circuit, is a sequential digital logic circuit which is not ruled by a clock circuit or global clock signal. As an alternative they always use signals that show completion of instructions and operations indicated by simple data transfer protocols. This type is varied from synchronous circuit in which variations to the signal values in the circuit are activated by repetitive pulses called a clock signal. However asynchronous circuits have the potential to be faster, and may also have different advantages in lesser power consumption, decreased electromagnetic interference, and better modularity in large a system which has active area of research in digital logic design. In asynchronous circuits, there is absence of clock and the state of the circuit variations as soon as the input changes. Since there is no necessary to wait for a clock pulse to begin process of the inputs, asynchronous circuits can be faster than synchronous circuits, and their speed is theoretically restricted only by the propagation delays of the logic gates. In principle, the asynchronous system achieves more advantages over synchronous systems: (i) lesser power, since an asynchronous component calculates only when necessary; (ii) higher performance, since global clock distribution and synchronization can be avoided and finally, (iii) greater modularity and ease of design, since there is absence of global timing constraints in the design.
There are countless designs of binary adders and here on asynchronous self-timed adders. Self-timed defines a logic circuits that be subject to on and/or engineer timing assumptions for the correct operation. Self timed adders have the capability to run faster averaged for dynamic data, as early completion sensing can avoid the need for the worst case bundled delay mechanism of synchronous circuits.
A. Pipelined Adders Using Single-Rail Data Encoding:
The asynchronous Req/Ack handshake can be used to enable the adder block as well as to generate the flow of carry signals over the circuit In most of the cases, a dual-rail carry convention is obtained for internal bit wise movement of carry outputs. These dual-rail signals can define more than two logic values (invalid, 0, 1), and that can be used to provide bit-level acknowledgment when a bit operation is completed. Final completion is sensed using all bit Ack signals are established at high. The carry-completion sensing adder is an example of a pipelined adder, which uses full adder (FA) functional blocks adapted for dual-rail carry. On the other hand, a speculative completion adder circuit is considered. It also called terminate logic and early completion to select the particular completion response from a number of fixed delay lines. However, the terminate logic implementation is exclusive due to the necessary of high fan-in requirements.
B. Delay Insensitive Adders Using Dual-Rail Encoding:
Delay insensitive (DI) adders are also asynchronous adders that provide bundling constraints or DI operations. Therefore, they can suitably operate in the existence of bounded but unknown gate and wire delays. There are many different DI adders, such as DI ripple carry adder (DIRCA) and DI carry look-ahead adder (DICLA). DI adders use dual-rail encoding and are likely to increase complexity. Though a dual-rail encoding doubles the wire complexity, they can still be used to produce circuits closely as effective as that of the single rail variants using dynamic logic or nMOS only designs. An example 40 transistors per bit DIRCA adder is considered in while the conventional CMOS RCA uses 28 transistors. Similar to CLA, the DICLA has carry propagate, generate, and terminate equations in terms of dual-rail encoding. They do not need connect the carry signals in a chain but organize them in a categorized tree. Thus, they can in fact operate faster when there is long carry chain. Fig 2 shows the general block diagram of PASTA.
An additional optimization is obtained from the performance that dual rail encoding logic can benefit from settling of either the 0 or 1 path. Dual-rail logic need not wait for two paths to be estimated. Thus, it is possible to speed up the carry look-ahead circuitry to send the carry-generate/carry-kill signals to any level in the tree. This is explained and referred as DICLA with speedup circuitry (DICLASP).
Fig 3 shows the adder first receives two input operands to perform half additions for each bit. Subsequently it iterate on using earlier created carry and sums to perform half-additions frequently until all carry bits are consumed and settled at zero level and complete the process.
A. Parallel Self Timed Adder:
The selection of input for two-input multiplexers resembles to the Req handshake signal and will be a single 0 to 1 transition symbolized by SEL. It will initially select the actual operands during SEL = 0 and also switch to feedback/carry paths for succeeding iterations using SEL = 1. The feedback path from the half adders enables the multiple iterations to last until the completion when all carry signals will assume zero values.
B. State Diagram:
Each state is represented by a ([C.sub.i+1] [S.sub.i]) pair where [C.sub.i+1][S.sub.i] Side note carry out and sum values respectively from the [i.sub.th] bit adder block. Fig 3 shows the two state diagrams are tense for the initial phase and the iterative phase of the projected architecture. During the initial phase the circuit simply workings as a combinational HA are operating in fundamental mode. It seems that due to the use of half adders in its place of full adders state (11) cannot appear. During the iterative phase (SEL = 1), the feedback path through multiplexer block is motivated using SEL. The carry transitions ([C.sub.i]) are allowable as many times as required to complete the recursion.
a) Initial Phase b) Iteration phase:
From the definition of fundamental mode circuits the present design cannot be measured as a fundamental mode circuit as the input-harvests will go through several transitions before producing the final output. That it is not a Muller circuit working external the fundamental mode either as internally several transitions will take place as shown in the state diagram. This is similar to cyclic sequential circuit where gate delays are used to separate individual states.
C. Recursive Formula for Addition:
Let [S.sub.ji] and [C.sub.ji+1] defines the sum and carry respectively for [i.sub.th] bit at the [j.sub.th] iteration. The initial condition ( j= 0) for addition is expressed by:
[S.sub.i.sup.0] = [a.sub.i][direct sum][b.sub.i] [C.sub.i+1.sup.0] = [a.sub.i] [b.sub.i] (1)
The [j.sub.th] iteration for the recursive addition is expressed by
[S.sub.i.sup.j] = [S.sub.i.sup.j-1][direct sum]0 [less than or equal to] i < n (2)
[C.sub.i+1.sup.j] = [S.sub.i.sup.j-1] [C.sub.i.sup.j-1] 0 [less than or equal to] i [less than or equal to] n (3)
The recursion is aborted at [k.sub.th] iteration when the following condition is met:
[C.sub.n.sup.k] + [C.sub.n-1.sup.k] + ... + [C.sub.1.sup.k] = 0, 0 [less than or equal to] k [less than or equal to] n. (4)
A CMOS implementation for the recursive circuit shown in Fig 4..For multiplexers and AND gates using the TSMC library executions while for the XOR gate we have used the faster ten transistor implementation based on transmission gate XOR to tie the delay with AND gates. The completion detection following is cancelled to provide an active high completion signal (TERM). This needs a large fan-in n-input NOR gate. Therefore an different more practical pseudo-nMOS ratioed design is used.
Using the pseudo-nMOS circuit the completion unit get out of the high fan-in problem as all the connections are parallel. The pMOS transistor connected to [V.sub.DD] of these ratioed design performances as a load register is concluded in static current drain when some of the nMOS transistors are on simultaneously. In addition to the [C.sub.i] the negative of SEL signal is also take in for the TERM signal to state that the completion cannot be accidentally turned on during the initial selection phase of the actual inputs. It also prevents the pMOS pull up transistor from being always on.
Hence static current will only be flowing for the duration of the actual computation. VLSI layout has also been estimated for a standard cell environment using two metal layers. The layout space provides 270 [lambda] x 130 [lambda] for 1-bit resulting in 1.123 M[[lambda].sup.2] area for 32-bit. The pulls down transistors of the completion detection logic are taken in the single-bit layout while the pull-up transistor is added along for the full 32-bit adder. It is nearly double the area required for RCA and is somewhat less than the most of the area effective prefix tree Brent Kung adder (BKA).The design works in a parallel manner for independent carry chain blocks it is varied as it employs feedback through XOR logic gates to constitute a single-rail cyclic asynchronous sequential adder.
Cyclic circuits can be more resource effective than their acyclic counterparts. On the other hand wave pipelining (or maximal rate pipelining) is a method that can apply pipelined inputs before the outputs become stable. The proposed circuit provides automatic single-rail pipelining of the carry inputs separated by propagation and inertial delays of the gates in the circuit path. Thus it is efficiently a single rail wave-pipelined approach and quite varied from conventional pipelined adders using dual-rail encoding to implicitly define the pipelining of carry signals.
A. Pasta design using dgmosfet:
Multiplexers are device that selects one of several analog or digital input signals and forwards the selected input into a single line. Multiplexers and AND gates are used by library design while for the XOR gate it uses the faster ten transistor implementation based on transmission gate XOR to tie the delay with AND gates. Memory-sharing partial parallel architecture provides a good balance on throughput and hardware cost in a large range. The calculation of critical path done which is equal for top and bottom leads to high clock frequency. Encoding is very useful to these LDPC codes because the number of incoming messages to each processing units are uniform diagonally the entire clock cycles.
Fig 5 shows the proposed block diagram of PASTA which has the performance analysis block to analyses the performance of the circuit.
B. Dual gate mosfet:
DGMOSFET is intended using lightly doped ultra-thin layers seem to be a very promising option for ultimate scaling of CMOS technology. Excellent short channel effect (SCE) immunity high trans conductance and ideal sub threshold factor have been providing by many theoretical and new studies on this device.
C. Structure of Dual Gate MOSFET:
The dual gate MOSFET is a form of MOSFET where two gates are made-up along the length of the channel one after the another. In this way, both gates disturb the level of current flowing between the source and drain channel. DGMOSFET is included of a conducting channel (usually undoped) surrounded by gate electrodes on both side. This accepts that no other part of the channel is far away from a gate electrode. In effect the dual gate MOSFET operation can be reflected equal to the two MOSFET devices in series shown in Fig 6. Both gates affect the overall performance of MOSFET operation and output. The dual gate MOSFET has referred astetrode construction where the two grids govern the current through the channel. The various gates control various sections of the channel which are in series with each other.
D. Design challenges:
Control of [V.sub.TT] is defined as the value of [V.sub.gs] which is obtained to cause surface inversion creating a conducting channel. Due to scaling of [V.sub.dd] we need to have reduced(~0.2 V) and symmetrical ([V.sub.Tn] = - [V.sub.Tp]) threshold voltages for both transistor types. For DGMOSFETs, [V.sub.t]T is primarily organized by [PHI] gate.. With a single mid gap material for both NMOS and PMOS symmetrical [V.sub.T] can be attained but the value is too large (~0.8 V).
E. Fabrication Issues:
Fabrication of the DGMOSFET is quite difficult. Arrangement of both gates is hard to achieve but it is needed for good device performance. A misaligned gate concludes in the extra capacitance and loss of current drive. Several different structures have been intended to deal with fabrication issues including planar and quasiplanar structures.
F. Advantages and Application:
Reduction of [I.sub.off]. Undoped channel reduces intrinsic parameter fluctuations and controls impurity scattering. Double gate affords for higher current drive capability and has better control of short channel effects. There are several applications of DGMOSFET in digital and in analog field such as reconfigurable gates which can perform multiple operations, variable gain amplifiers, high frequency mixers etc.
LT spice is analog circuit simulator within corporate schematic capture and waveform viewer in the tool. It was explicitly written to outperform analogous tools for sale fromsoftwarecompaniesinthenecessityofbeingusedforin-houseICdesignaspart of Linear Technology Corporation's competitive advantage as semiconductor company.
The Fig 7 shows the implementation of parallel self timed adder using DGMOS.
Component Power consumption CMOS -6.802 mw DGMOS -134.262 Tw
Thus the parallel self timed adder is aimed by combining the modules using DGMOS which has a better performance over the CMOS. And the result shows thus the power consumption in the circuit is decreased while using dual gate MOSFETs.
This brief presents an efficient design of PASTA by combining the modules using DGMOSFET. Thus the DGMOS circuit works in a parallel manner for independent carry chains, and thus provides logarithmic average time performance over random input values. The completion detection unit for the projected adder using dual gate MOSFET is also practical and efficient. Simulation results are used to validate the advantages of the proposed design.
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(1) Ms.R. Vigneshwari, (2) Mr.T.Jayasimha and (3) Mr.P.Sasikumar
(1) PG student, Department of ECE, Vivekanandha College of Engineering for women, Tiruchengode
(2,3) Assistant Professor, Department of ECE, Vivekanandha College of Engineering for women, Tiruchengode Assistant Professor, Department of ECE, Vivekanandha College of Engineering for women, Tiruchengode
Received 28 January 2017; Accepted 22 March 2017; Available online 28 April 2017
Address For Correspondence:
Ms.R. Vigneshwari, PG student, Department of ECE, Vivekanandha College of Engineering for women, Tiruchengode.
Caption: Fig. 1: Parallel adders.
Caption: Fig. 2: General block diagram of PASTA.
Caption: Fig. 3: State diagrams for PASTA.
Caption: Fig. 4: CMOS implementation of PASTA.
Caption: Fig. 5: Block diagram of proposed system.
Caption: Fig. 6: Dual gate MOSFET.
Caption: Fig. 7: Combining the modules of PASTA using DGMOS.
Caption: Fig. 8: Average power consumption using DGMOS.
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|Title Annotation:||Double Gate Metal Oxide Semiconductor Field Effect Transistor|
|Author:||Vigneshwari, R.; Jayasimha, T.; Sasikumar, P.|
|Publication:||Advances in Natural and Applied Sciences|
|Date:||Apr 30, 2017|
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