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Plastics; the sine qua non of electronics packaging.

Plastics: The Sine Qua Non of Electronics Packaging

For applications ranging from inexpensive consumer electronics to sophisticated computing systems, the use of plastic packaging within the electronics industry continues to grow. The inside of a typical personal computer, for example, contains dual-in-line packages (DIPs), plastic-leaded chip carriers (PLCCs), and plastic pin-grid arrays (PPGAs) for chip carriers. Applications for plastic dielectric materials include inexpensive chip carriers manufactured by tape-automated bonding (TAB), and the manufacture of cables that interconnect circuit boards. For purposes of encapsulation, plastics satisfy a wide range of physical materials requirements, which are in turn driven by the packaging requirements of density, reliability, and low cost (see the Table). Plastics are used as dielectric materials in cables and TAB packages because of several characteristics: They are inexpensive, flexible, and have favorable dielectric constants; they withstand breakdown under applied voltage; and they are mechanically stable, which eases their processing by photolithographic techniques. This article describes various plastic packages for electronics application.

Table : In Electronics Applications, Packaging Requirements Determine Materials Requirements.
Packaging Materials
requirements requirements
Density Dimensional stability
 Low dielectric constant
 Fine-line processing
Reliability Thermal stability
 High purity
 Low mechanical stress
 Resistance to high
Cost Ease of processing
 Material cost

Electronics Packaging

The art of electronics packaging for computers consists in interconnecting or providing electrical paths between components while ensuring their mechanical integrity and protection from the environment. Packaging must also allow for thermally conductive paths that permit the dissipation of heat.

Packaging of the integrated circuit chip, which forms the foundation of the modern electronic computer, is referred to as first-level packaging. The second-level package is the board on which the chips are mounted; progressively higher levels culminate at the box-level package.

The number of circuits that can be fabricated on the surface of a silicon substrate, the area of which typically measures approximately 1.0[cm.sup.2], has grown to the tens of thousands for logic chips. For memory chips, the number is in the millions, reflecting an exponential rate of growth: The number of circuits has multiplied by four approximately every two years. As the number of circuits on the chip increases, so does the number of I/O leads (input/output pins) required to make use of the circuits. Known as Rent's Rule, the relationship between the required number of I/Os and the circuit is logarithmic (Ref. 1). Within a family of semiconductor chips, for example, a chip possessing 1000 circuits may require 40 I/Os. However, a chip possessing 10,000 circuits needs 100 I/Os; one with 100,000 circuits, 250 I/Os. As the number of circuits on the chip and the number of I/Os needed to make use of the circuits increase, so must the packaging of the chips evolve to accommodate this growth.

Chip Packaging

Performance, density, and mechanical requirements limit the useful size of a given type of package. Figure 1 shows size vs. lead count of several of the more popular varieties of plastic package: the DIP, PLCC, PPGA, and TAB (Ref. 2). Solving the problem of increasing I/O number or lead count requires moving to packages of increasing area density or smaller lead-to-lead pitch: from the DIP of 100-mil lead pitch to the PLCC of 50-mil lead pitch to the TAB package of 10-mil lead pitch (1.0 mil = 25.4 um). Examples of these packages are shown in Figs. 2, 3, and 4. With denser packaging come changes in the technology used in the packaging process.

The Molded Plastic


Figure 2 shows the DIP and the PLCC (Ref. 3). These and other plastic packages such as the quad flatpack (QFP) and the small-outline package (SOP) are manufactured by similar processes. The DIP varies from the other packages to the extent that its I/O pins are designed to penetrate the board to which they are soldered; it is thus a pin-in-hole (PIH) component. The other components are soldered to the surface of the board by means of surface-mount technology (SMT), which can provide greater density. The DIP is generally used for packages of approximately 60 leads or fewer; the PLCC, for packages of up to 100 leads. The QFP, which is similar to the PLCC but has a denser I/O array of gullwing leads, is typically used for packages of 150 leads.

The manufacturing process begins with a rigid lead frame, typically stamped from a 10-mil-thick metal such as copper or Alloy 42, which consists of 42% nickel and 58% iron. The back of the diced chip can be soldered to the center of the leadframe with a gold-silicon eutectic solder. It can also be bonded to the center of the leadframe with a filled thermally conductive epoxy. By means of wirebonding, electrical connections are made between the aluminum-alloy pads (on the chip) and the leadframe. An automatic tool applies ultrasonic vibration and pressure to bond the ends of a thin 1-mil gold wire to the chip pad at one end and the leadframe at the other end; heat may be used to form either thermosonic or thermo-compression bonds. Then, the package is encapsulated in plastic by means of transfer molding - a thermosetting polymer, such as a filled epoxy, may be used as the encapsulation material. The encapsulation plastic flows at room temperature, but reacts to heat by forming a crosslinked network that cannot be remelted. Molds may be designed to accommodate several hundred packages at once.

The plastic molding compound is formulated to have the following properties: high purity with respect to corrosive contaminants such as chloride and sodiumions; excellent adhesion to a variety of materials including silicon, leadframe metal, and the chip passivation; impermeability to moisture and low moisture absorption; rigidity, so as to withstand handling; heat resistance, so as to withstand soldering to the board; ease of processing; and low costs. Typical epoxy formulations contain an epoxy resin and a hardener, an accelerator or catalyst for the epoxy-hardener reaction, an inorganic filler, coupling agents to bond the epoxy to the filler, flame retardants, a mold release agent, and a black coloring agent.

The plastic Pin Grid Array

The substrate for the PPGA may be made in the same manner as that of printed circuit cards; molding is an alternative. In the first process, copper is laminated to epoxy-fiberglass sheets and etched to form the circuit fan-out pattern. To facilitate wirebonding, the copper is gold plated. Holes are drilled through the substrate and plated through at the positions of the pins. Pins are inserted into the holes and soldered to the fan-out pattern. Next, the chip is bonded to the substrate with a low-temperature curing adhesive; wirebonding of the electrical connections in a manner similar to that of the molded plastic packages follows. To seal the package, a plastic frame is placed around the chip and wirebonds, and the enclosed area is filled with a liquid encapsulant, such as an epoxy or silicone. A plastic or metal cap is then used to cover the face of the substrate. Figure 3, shows the package. The PPGA, like the DIP, is a PIH (pin-in-hole) package; however, its multiple-row I/O array makes it competitive with peripheral-I/O array packages that have smaller lead pitch. A typical application for the PPGA is a package for a 100- to 200-I/O microprocessor chip.

The TAB Package

Tape-automated bonding, used to manufacture chip carriers such as the one shown in Fig. 4, permits the packaging of chips of up to 500 leads. The tape for the TAB package is defined by means of photolithography and handled in a reel-to-reel format, thus facilitating automated processing and reducing costs. It may be obtained in a 35-mm format, and it consists of a thin (typically 2 mills) polymer substrate, usually of polyimide, and a thin (typically 1.4 mil) metal leadframe, usually of tin- or gold-plated copper. In one TAB process, both polyimide and copper are defined by photolithography to produce inner leads as small as 2 mils wide. The chip is prepared for bonding to the metal leadframe through a process by which gold bumps are plated onto the chip bonding pads. Unlike wirebonding, and while the packages are in the tape format, all the inner leads are bonded simultaneously to the chip by means of thermocompression bonding.

As in the case of other plastic packages, an encapsulant is needed to protect the inner-lead bonds and the chip from environmentally caused mechanical damage. Transfer molding, or encapsulation by an epoxy or silicone material of the chip face alone, will ensure such protection (Ref. 4). Thus, the TAB package may be tested while still on the tape. For board mounting, the package is cut from the tape and the outer leads are soldered to the surface of the board; the procedure is known as outer-lead bonding. For additional protection, a coating may be applied over the TAB package after card mounting. The pitch of the outer leads may be as small as 10 mils; a TAB package that is 2.5 cm on a side can accommodate as many as 400 leads. By comparison, a typical DIP of the same area is capable of carrying about one tenth this number of I/Os.


Advances in technology are producing circuit chips with ever-increasing numbers of leads to be packaged. Demands on density and performance have led the electronics industry to find the means to package these chips in small inexpensive packages. Because of low cost and ease of processing, plastics have found wide application in solving the problems of electronics packaging. Additional information on plastic packaging for electronics may be found in Refs. 2, 3, 5, and 6.

PHOTO : Package size vs. number of input/output leads for several types of plastic packages (from Ref. 2 by permission).

PHOTO : Two plastic packages, the dual-in-line (left) and the plastic-leaded chip carrier (right), are encapsulated in a thermosetting polymer by means of transfer molding (from Ref. 3 by permission).

PHOTO : A surface view (left) and a cross section (right) of the plastic pin-grid array, a typical application for which is a package for a 100-to 200-I/O microprocessor chip (From Ref. 3 by permission).

PHOTO : Like other plastic packages, a tape-automated bonding (TAB package is encapsulated to protect the chip and inner-lead bonds from environmentally caused mechanical damage.

References and


[1.] B.S. Landman and R.L. Russo, "On a Pin Versus Block Relationship for Partitions of Logic Graphs," IEEE Tr. Computers, vol C-20, p. 1469 (1971). [2.] M.F. Bregman and C.A. Kovac, "Plastic Packaging for VLSI-Based Computers," Solid State Technology, vol. 31 (6), p 75 (1988). [3.] C.A. Kovac, "Plastic Package Fabrication," Electronic Materials Handbook, vol. 1, ASM International, Metals Park, Ohio (1989). [4.] K. Fujita, et al., "Chip-size Plastic Encapsulation on Tape Carrier Package," Int. J. Hyb, Microelectron., vol. 8 (2), p. 9 (1985). [5.] R.R. Tummala and E.J. Rymaszewski, eds., Microelectronics Packaging Handbook, Van Nostrand Reinhold, New York (1989). [6.] D.R. Seraphim, R.C. Lasky, and C.-Y. Li, eds., Principles of Electronic Packaging, McGraw-Hill, New York (1989).
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Author:Moskowitz, P.A.; Kovac, C.A.
Publication:Plastics Engineering
Date:Jun 1, 1990
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