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Philips Introduces New CMOS Technique.

Netherlands contractor Philips Semiconductors has introduced an enhanced 0.18 [micro]m complementary metal oxide semiconductor (CMOS) fabrication technique that uses low dielectric, constant dielectrics, an additional local interconnection metal layer and new high density memory cells. Designated the CMOS18, the technique utilises a combination of metal layers with low sheet resistivity and a hydrogen silsesquioxane-based flowable oxide as the insulating layer, a combination that may significantly reduce parasitic capacitance, thereby shortening propagation delays. The conventional metal-dielectric-metal and metal-dielectric-semiconductor structures create parasitic capacitance that must be charged and discharged every time a logic signal propagates from one part of the IC to another, thereby slowing down chip performance. In order to maximise on-chip gate densities, the CMOS18 technique makes use of an additional local interconnect layer that is added to the six metal layers normally found in a 0.18 [micro] m CMOS device. Positioned below the normal metal layers at gate level, the new layer is made of tungsten and is capable of achieving conductor widths as low as 0.24 [micro]m. So configured, a local-interconnect-layer-equipped device is claimed to offer up to 20 percent silicon area improvement for typical core cells. To enhance device memory and chip density, CMOS18 devices include a special high density SRAM cell. The capability will be further enhanced via a high density dual-port SRAM cell, which is currently under development by the company. A Flash memory cell option is available for use in telecommunications and smart card applications. This option is based on stacked-gate technology and is significantly smaller than 0.8 [micro][m.sup.2] in area. The company is also migrating recently acquired VLSI technology cell libraries to the CMOS18 process in order to provide customers with the benefits of a very broad application-specific IC (ASIC) design library, advanced ASIC design tools and short development cycles.

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Title Annotation:Philips Semiconductors' complementary metal oxide semiconductor manufacturing technology
Comment:Philips Introduces New CMOS Technique.(Philips Semiconductors' complementary metal oxide semiconductor manufacturing technology)
Publication:Microwave Journal
Article Type:Brief Article
Geographic Code:4EUNE
Date:Jan 1, 2000
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