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Phase disposition PWM based Reduced Switch Reverse Voltage multi level inverter.

INTRODUCTION

The demand for high power AC drives has been increased in the recent years. High power AC drives are typically connected to the medium-voltage network. It is tough to connect a single power semiconductor switch directly to the medium-voltage network. For these reasons, a family of new Multi Level Inverters (MLIs) has emerged as the answer for high power medium or high voltage applications. It has gained growing knowledge in industry and research since it was introduced in 1980s [1]. A MLI is an interconnection of number of power semiconductor devices. The advantages of this method over the usual two-level inverter approach are: improved power quality, reduced voltage stress on the switches and load, improved amplitude of fundamental components and lower electromagnetic interference [2]. The basic role of MLI is to sum up several small DC sources with suitable switching sequences to the array of power switches so as to obtain a multiple steps stair-case waveform which resembles the AC sinusoidal waveform. Hence inverter operation is achieved. The merits of the MLI can be enhanced by increasing the number of steps in the output waveform.

There are three types of commonly used MLI topologies: Neutral Point Clamped (NPC) [3], Flying Capacitor (FC) [4] and Cascaded H-Bridge (CHB) [5] multi level inverter. Among these topologies CHB Multi Level Inverter (CHBMLI) becomes more attractive, because of its greater reliability arising from its modularity and lesser number of hardware components. Cascade connection of a number of basic H-bridge inverters forms a CHBMLI. Each H-bridge inverter can generate three voltage levels in the output. These inverters are classified as: symmetric (each H-bridge is fed by equal DC sources) and asymmetric (each H-bridge is fed by unequal DC sources) MLIs. An asymmetric CHBMLI is preferred to produce more number of output levels with same number of power switches. Conventionally, there are two asymmetrical configurations: binary and ternary. There are various other asymmetrical MLI topologies proposed by many researchers [6]. Since the MLI topologies require reduced voltage stress on the power switching devices, we can realize the high power inverters with low power matured semiconductor technology [7]. MLIs have been used in many applications, such as variable speed AC drives, power quality devices and renewable energy generation such as photovoltaic, wind and fuel cells [8]-[10].

The power quality of the MLI increases as the number of levels in the output increases. The main disadvantage of MLI is the circuit complexity increases when the output levels increases, hence the overall cost and size of the system. To overcome these disadvantages, many topologies are introduced with reduced number of components [11]-[15]. Another major disadvantage with the conventional MLI is the requirement of small isolated DC voltage sources or series bank capacitors. This is overcome by using the renewable energy sources.

The performance of the MLI is mainly depends on the modulation technique used to generate the required gating signals. Different modulation techniques have been introduced to improve the performance of the MLIs [2], [10], [16]-[19]. The commonly used modulation techniques are Selective Harmonic Elimination (SHE) [16], [17], Carrier Based PWM (CBPWM) [18] and Space Vector Modulation (SVM) [19].

In this paper, a Reduced Switch Reverse Voltage (RSRV) multi level inverter with asymmetrical DC sources and reduced number of components is considered. This topology requires lesser number of components than the conventional topologies. The performance of the inverter is enhanced by a Multi Carrier based Pulse Width Modulation (MCPWM). The various MCPWM methods are discussed and Phase Disposition Pulse Width Modulation (PDPWM) based 9-level RSRV-MLI is developed. The operation and performance of the 9level RSRV-MLI with asymmetrical DC sources are presented and validated through the simulation results.

2. Structure of RSRV-MLI Topology:

Cascade connection of number of sub-modules forms a Reduced Switch Reverse Voltage (RSRV) MLI topology to produce the required multi level output voltage. The generalized block diagram of asymmetrical RSRV-MLI with reduced components is shown in Fig. 1. This topology can be easily extended to higher levels by adding the number of sub-modules. Each sub-module consists of two power switches and one DC voltage source. The switches in one sub-module should not be triggered simultaneously. All the DC voltage sources are asymmetrical and it follows the voltage ratios 1:[2.sup.0]: [2.sup.1]: ... : [2.sup.(n-2)].

The block diagram shown in Fig. 1 consists of two parts, one is magnitude generator or level generator which forms by the cascade connection of number of basic sub-modules (SM) and the other is polarity generator which is the basic H-bridge (HB) circuit. The magnitude generator part is responsible to produce the all possible positive voltage levels (unidirectional staircase waveform) of the output by proper switching function of switches in the magnitude generator part. This unidirectional staircase waveform is applied to the polarity generator part. The polarity generator part provides the alternative polarities to the output of the magnitude generator. So that the alternating output voltage is obtained. The switches in the polarity generator part are operated at the fundamental or line frequency.

The number of output levels with 'n' number of asymmetrical sources is given by,

N = [2.sup.n] + 1 (1)

The number of sub-modules (m) required is calculated by,

m = n - 1 (2)

The maximum output voltage obtainable is given by,

V = (N - 1)/2 x [V.sub.dc] (3)

The number of switches required for this topology with asymmetrical DC sources is given by,

[N.sub.sw] = 2m + 4 [congruent to] [log (N - 1) - 0.301/0.1505] + 4 (4)

The number of driver circuits ([N.sub.dri]) required is equal to the number of switches ([N.sub.sw]) required.

2.1 Description of RSRV-MLI Topology:

The operation of asymmetrical 9-level RSRV-MLI topology with reduced components is explained with the help of the circuit diagram shown in Fig. 2. The circuit diagram of this topology can be divided into two parts, one is magnitude generator part or level generator part other one is polarity part. For 9-level RSRV-MLI, it requires three asymmetrical DC voltage sources ([V.sub.dc1], [V.sub.dc2], [V.sub.dc3]), two sub-modules ([SM.sub.1], [SM.sub.2]) and one H-bridge module (HBM). The magnitudes of DC sources are 55 V, 55 V and 110 V.

The switches in the magnitude generator parts are operated at the higher frequency (higher than the fundamental frequency) to produce all possible positive output voltage levels by proper switching sequence of switches in the magnitude generator part ([S.sub.ax] and [S.sub.bx]). Here each sub-module contains two power switches. These two switches of each sub-module should not be triggered simultaneously. By proper switching of the switches in the magnitude generator, various possible positive output voltage levels (55 V, 110V, 165 V and 220V) can be achieved. This produces the unidirectional staircase waveform ([V.sub.mg]). The polarity generator is just an H-bridge module. The function of this polarity generator is to change (reverse) the polarity of the output for every half cycle so that the bidirectional staircase waveform can be achieved. Switches S[H.sub.1] & S[H.sub.2] are turned ON during positive half cycle, SH3 & SH4 are turned ON during negative half cycle and for zero output level, the switches (S[H.sub.1] & S[H.sub.3]) or (S[H.sub.2] & S[H.sub.4]) are turned ON. The switches at polarity generator are operated at the fundamental frequency. Switching sequences of the asymmetrical 9-level RSRV-MLI is given in the TABLE 1.

3 Multi Carrier Based Pulse Width Modulation:

To enhance the quality of the MLI output, various modulations are used. Out of these modulation methods, SHE or CBPWM methods are most commonly used because of ease of controllability. In this paper, Phase Disposition PWM (PDPWM) of carrier based modulation is considered. This PDPWM method is more suitable for inverter operation, its output contains only the odd harmonics (all even harmonics are absent) and the maximum harmonic energy is mitigated to the frequency which is equal to the carrier frequency. In PDPWM method, several triangular carrier signals are compared with one sinusoidal reference signal. The number of carriers required to produce N-level output is (N-1).

The single sinusoidal reference waveform has peak to peak amplitude of [A.sub.r] and a frequency [f.sub.r]. The multiple triangular carrier eaves are having same peak to peak amplitude [A.sub.c] and frequency [f.sub.c]. The single sinusoidal reference signal is continuously compared with all the carrier waveforms. A pulse is generated, whenever the sinusoidal reference signal is greater than the carrier signal. The frequency modulation index ([m.sub.f]) is as follows

[m.sub.f] = [f.sub.c]/[f.sub.r] (5)

Fig. 3 illustrates the PDPWM strategy, where the carriers with same frequency [f.sub.c] and same peak to peak amplitude [A.sub.c] but they are level shifted. The amplitude modulation index of the PDPWM is given by

[m.sub.a] = [A.sub.r]/(N - 1)[A.sub.c] (6)

Fig. 4 shows the functional block diagram of the PDPWM strategy. It requires eight carrier signals and one sinusoidal signal to produce the required switching sequences for 9-level output voltage. These carrier signals are continuously compared with the reference signal and produce the modulated control signals. These control signals are combined by the proper combinational logics formed by (7)-(14) and produces the sequence of switching pulses required for the 9-level RSRV-MLI.

[G.sub.H1] = ([P.sub.11] + [P.sub.22] + [P.sub.33] + [P.sub.44]) [S.sub.1] (7)

[G.sub.H2] = ([P.sub.11] + [P.sub.22] + [P.sub.33] + [P.sub.44]) [S.sub.2] (8)

[G.sub.H3] = ([P.sub.11] + [P.sub.22] + [P.sub.33] + [P.sub.44]) [S.sub.3] (9)

[G.sub.H4] = ([P.sub.11] + [P.sub.22] + [P.sub.33] + [P.sub.44]) [S.sub.4] (10)

[G.sub.a1] = ([P.sub.11] [direct sum] [P.sub.22]) + ([P.sub.33] [direct sum] [P.sub.44]) (11)

[G.sub.b1] = ([P.sub.11][P.sub.22]) + ([P.sub.33] [direct sum] [P.sub.22]) (12)

[G.sub.a2] = [P.sub.22] [direct sum] [P.sub.44] (13)

[G.sub.b2] = [P.sub.22] (14)

where, [G.sub.H1], [G.sub.H2], [G.sub.H3] and [G.sub.H4] are the switching pulses applied to the switches [H.sub.1], [H.sub.2], [H.sub.3] and [H.sub.4] in the polarity generator part. [G.sub.a1] and [G.sub.b1] are the switching pulses applied to the switches in the first sub-module ([SM.sub.1]) of the level generator part. [Ga.sub.2] and [Gb.sub.2] are the switching pulses applied to the switches in the second sub-module ([SM.sub.2]) of the level generator part. [S.sub.1], [S.sub.2], [S.sub.3] and [S.sub.4] are the pulses produced by the zero crossing detector part. The pulses [P.sub.1]-[P.sub.8] are produced by the PDPWM generation part. The pulses [P.sub.11], [P.sub.22], [P.sub.33] and [P.sub.44] are derived from the pulses [P.sub.1]-[P.sub.8].

4 Results and Discussions:

The feasibility of the PDPWM based 9-level RSRV-MLI is studied through the simulations carried out using MATLAB/Simulink. The Simulink model developed for the presented topology is shown in Fig. 5. For 9-level RSRV-MLI, two sub-modules (SM1 & SM2) and one polarity generator module (HBM) were used. The gating pulses for the switches used in the power circuit were generated by comparing the carrier signals and reference signal shown in Fig. 3. The functional block diagram of the PDPWM based pulse generation circuit is shown in Fig. 4. The simulation parameters used for PDPWM based 9-level RSRV-MLI are shown in Table 2. The pulses used in polarity generator part and level generator part are shown in Fig. 6. It is clear that the switches in the polarity generator part are operated at the fundamental frequency and the switches in the level generator part are operated at the higher frequency.

The output voltage and current waveforms of the PDPWM based 9-level RSRV-MLI with R-load are shown in Fig. 7. From the figure, it is clear that the output waveforms contain all the possible levels ([+ or -] 55V, [+ or -] 110V, [+ or -] 165V, [+ or -] 220V and 0V) as anticipated, also the voltage and current waveforms are in phase. The harmonic analysis of these output waveforms shows that the voltage and current THDs are 9.12%. The harmonic spectrum of the output voltage is shown in Fig. 8. From the harmonic spectrum, it is observed that it contains only the odd numbered harmonics and also the maximum harmonic energy occurred at the carrier frequency. The magnitude of all the lower order harmonics are lesser that 3%. The peak value of output voltage and current are 219V and 0.219A.

The output voltage and current waveforms with RL-load is shown in Fig. 9. With RL-load the output voltage waveform contains all the possible nine levels in the output, whereas the output current is smooth sine wave with some phase shift. Fig. 10 shows the harmonic spectrums of the output voltage and current of PDPWM based 9-level RSRV-MLI with RL-load. From these harmonic spectrums, it is clear that the THDs of output voltage and current are 9.24% and 0.9% respectively. The output voltage and current waveforms contains odd harmonics only and the maximum harmonic energy occurred at the frequency equal to the carrier frequency.

Fig. 11 shows the harmonic spectra of PDPWM based 9-level RSRV-MLI for different even valued frequency modulation index ([m.sub.f]) and [m.sub.a]=1. This figure is evident that the output contains both odd and even numbered harmonics. Fig. 12 shows the harmonics spectra of PDPWM based 9-level RSRV-MLI for different odd valued frequency modulation index ([m.sub.f]) and [m.sub.a]=1. This figure is an evident that the output contains only odd numbered harmonics. Fig. 13 shows the harmonic spectra of PDPWM based 9-level RSRV-MLI for different amplitude modulation index ([m.sub.a]) and [m.sub.f]=25. Form the Fig. 13, it is clear that the output contains only odd numbered harmonics. In all the above cases of PDPWM based inverter the maximum amount of harmonic energy is present at the frequency which equal to the carrier frequency. The values of the individual harmonics are given in the APPENDIX. The performance of the PDPWM based 9-level RSRV-MLI for [m.sub.f]=25 and [m.sub.a]=1.0 are summarized in Table 3.

Conclusions:

In this paper, a PDPWM based 9-level RSRV multi level inverter topology with reduced number of components was effectively developed. This inverter requires lesser number of components when it is used for higher number of output levels. A multi carrier based PDPWM scheme is demonstrated. This PDPWM with odd number of frequency modulation index produces the odd numbered harmonics only in the output of the inverter and all the lower order harmonics are well within the limit of IEEE-519 standard. Also the maximum harmonic energy is dissipated at the carrier frequency. The presented inverter topology required lesser number of components, could promise better performance, reliability and reduction in size and cost of the inverter. The performances of the PDPWM based 9-level RSRV-MLI are demonstrated with the simulation results.

REFERENCES

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[7.] Mastromauro, R.A., M. Liserre, A. Dell' Aquila, 2012. Control Issues in Single-Stage Photovoltaic Systems: MPPT, Current and Voltage Control. IEEE Trans. Ind. Informatics, 8(2): 241-254.

[8.] Karthikeyan, V., V. Jamuna, Abisha James, 2014. Multilevel Inverter for Hybrid Energy Generation System," Applied Mechanics and Materials, 622: 127-131.

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[10.] Najafi, E., A.H.M. Yatim, 2012. Design and Implementation of a New Multilevel Inverter Topology. IEEE Tran. Ind. Electron., 59(11): 4148-4154.

[11.] Karthikeyan, V., V. Jamuna, 2013. Hybrid Control Strategy for BCD Topology Based Modular Multilevel Inverter. Circuits and Systems, 7(8): 1441-1454.

[12.] Banaei, M.R., E. Salary, 2013. Asymmetric Cascaded Multi-level Inverter: A Solution to Obtain High Number of Voltage Levels. Journal of Electrical Engineering & Technology, 8(2): 316-325.

[13.] Rakesh Kumar, V. Karthikeyan and V. Jamuna, 2013. A Multilevel Inverter with Reduced Number of Switches. Procedings of Second National Conference on Power System Power Electronics and Drives (PSPED-2013): 125-130.

[14.] Babaei, E., S. Laali, Z. Bayat, 2015. A Single-Phase Cascaded Multilevel Inverter Based on a New Basic Unit with Reduced Number of Power Switches. IEEE Trans. Ind. Eelctron., 62(2): 922-929.

[15.] Babaei, E., S. Laali, S. Alilu, 2014. Cascaded Multilevel Inverter with Series Connection of Novel H-Bridge Basic Units. IEEE Trans. Ind. Electron., 61(12): 6664-6671.

[16.] Ghasemi, N., F. Zare, A.A. Boora, A. Ghosh, C. Langton, F. Blaabjerg, 2012. Harmonic Elimination Technique for a Single-Phase Multilevel Converter with Unequal DC Link Voltage Levels. IET Power Electron., 5(8): 1418-1429.

[17.] Kumle, A.N., S.H. Fathi, F. Jabbarvaziri, M. Jamshidi, S.S.H. Yazdi, 2015. Application of Memetic Algorithm for Selective Harmonic Elimination in Multi-Level Inverters. IET Power Electron., 8(9): 1733-1739.

[18.] McGrath, B.P., D.G. Holmes, T. Lipo, 2002. Multicarrier PWM Stategies for Multilevel Inverter. IEEE Trans. Ind. Electron., 49(4): 858-867.

[19.] Irfan, A., B.B. Vijay, 2014. Simplified Space Vector Modulation Technique for Seven-Level Cascaded HBridge Inverter. IET Power Electron., 7(3): 604-613.
APPENDIX--I:

Harmonic Analysis for PDPWM based 9-level RSRV-MLI

Parameters      Values

[m.sub.a]       0.95     0.9     0.85    0.8     1.0     0.9
[m.sub.f]       25       25      25      25      27      27
%THD            15.39    16.57   16.90   17.34   13.66   16.61

Fundamental
voltage in pu   0.95     0.9     0.85    0.8     1.0     0.9
[V.sub.01]

Magnitude of voltage Harmonics (in % of fundamental)

[V.sub.1]       100      100     100     100     100     100
[V.sub.2]       0        0       0       0       0       0
[V.sub.3]       2.05     1.15    1.44    0.74    1.62    0.91
[V.sub.4]       0        0       0       0       0       0
[V.sub.5]       1.36     1.95    2.1     1.7     1.56    1.67
[V.sub.6]       0        0       0       0       0       0
[V.sub.7]       0.48     1.07    1.81    1.72    0.25    1.92
[V.sub.8]       0        0       0       0       0       0
[V.sub.9]       0.8      1.26    0.37    1.28    0.81    0.55
[V.sub.10]      0        0       0       0       0       0
[V.sub.11]      0.8      0.34    1.67    0.76    0.01    1.36
[V.sub.12]      0        0       0       0       0       0
[V.sub.13]      0.4      1.48    1.22    0.62    0.92    0.2
[V.sub.l4]      0        0       0       0       0       0
[V.sub.l5]      1.09     0.47    1.45    2.14    0.38    1.73
[V.sub.l6]      0        0       0       0       0       0
[V.sub.l7]      0.98     0.05    0.86    0.67    0.51    0.06
[V.sub.l8]      0        0       0       0       0       0
[V.sub.l9]      0.19     1.31    1.08    0.17    1.49    0.04
[V.sub.20]      0        0       0       0       0       0
[V.sub.21]      0.12     0.88    0.78    1.09    1.02    0.87
[V.sub.22]      0        0       0       0       0       0
[V.sub.23]      0.94     1.26    0.59    1.11    1.51    1.09
[V.sub.24]      0        0       0       0       0       0
[V.sub.25]      11.12    12.24   11.89   11.57   0.89    1.27
[V.sub.26]      0        0       0       0       0       0
[V.sub.27]      1.96     1.79    0.98    1.15    9.12    12.24
[V.sub.28]      0        0       0       0       0       0
[V.sub.29]      1.96     2.16    1.83    1.61    1.47    1.41
[V.sub.30]      0        0       0       0       0       0
[V.sub.31]      0.68     2.36    2.61    2.23    2.52    1.61
[V.sub.32]      0        0       0       0       0       0
[V.sub.33]      1.89     0.59    1.17    2.32    1.42    2.25
[V.sub.34]      0        0       0       0       0       0
[V.sub.35]      1.27     1.67    2.37    2.37    1.91    1.7

Parameters      Values

[m.sub.a]       0.8     1.0     0.9     0.8     1.0     0.9
[m.sub.f]       27      29      29      29      31      31
%THD            17.15   13.62   16.73   16.94   13.76   16.62

Fundamental
voltage in pu   0.8     1.0     0.9     0.8     1.0     0.9
[V.sub.01]

Magnitude of voltage Harmonics (in % of fundamental)

[V.sub.1]       100     100     100     100     100     100
[V.sub.2]       0       0       0       0       0       0
[V.sub.3]       0.03    0.59    0.73    0.12    0.38    0.12
[V.sub.4]       0       0       0       0       0       0
[V.sub.5]       0.47    1.39    0.77    0.03    0.88    0.21
[V.sub.6]       0       0       0       0       0       0
[V.sub.7]       1.7     1.81    1.03    1.02    1.52    0.86
[V.sub.8]       0       0       0       0       0       0
[V.sub.9]       2.18    0.3     1.91    2.18    1.45    1.43
[V.sub.10]      0       0       0       0       0       0
[V.sub.11]      1.57    1.2     0.89    2.15    0.1     2.09
[V.sub.12]      0       0       0       0       0       0
[V.sub.13]      0.96    0.14    1.15    1.47    0.98    1.0
[V.sub.l4]      0       0       0       0       0       0
[V.sub.l5]      0.84    1.26    0.01    1.12    0.06    1.21
[V.sub.l6]      0       0       0       0       0       0
[V.sub.l7]      2.01    0.04    1.57    0.99    1.25    0.34
[V.sub.l8]      0       0       0       0       0       0
[V.sub.l9]      0.72    0.39    0.59    1.81    0.01    1.43
[V.sub.20]      0       0       0       0       0       0
[V.sub.21]      0.04    1.47    0.11    1.03    0.36    0.47
[V.sub.22]      0       0       0       0       0       0
[V.sub.23]      0.97    1.2     1.26    0.05    1.33    0.2
[V.sub.24]      0       0       0       0       0       0
[V.sub.25]      0.99    1.24    1.01    1.04    1.28    1.02
[V.sub.26]      0       0.01    0.01    0       0       0
[V.sub.27]      11.35   0.94    1.1     0.88    1.29    0.99
[V.sub.28]      0       0       0       0       0       0
[V.sub.29]      1.04    9.05    12.4    11.12   0.99    1.27
[V.sub.30]      0       0.01    0.02    0.01    0       0
[V.sub.31]      1.0     1.12    1.1     0.87    9.19    12.26
[V.sub.32]      0       0.01    0       0       0       0
[V.sub.33]      1.16    1.79    1.14    1.04    0.96    1.23
[V.sub.34]      0       0       0       0       0       0
[V.sub.35]      2.32    2.14    1.75    0.41    1.45    1.05

Parameters      Values

[m.sub.a]       0.8     1.0     1.0     1.0
[m.sub.f]       31      26      28      30
%THD            17.03   13.26   13.79   13.44

Fundamental
voltage in pu   0.8     1.0     1.0     1.0
[V.sub.01]

Magnitude of voltage Harmonics (in % of fundamental)

[V.sub.1]       100     100     100     100
[V.sub.2]       0       1.9     0.88    0.23
[V.sub.3]       0.01    0.01    0       0.01
[V.sub.4]       0       2.05    1.34    0.67
[V.sub.5]       0.7     0.01    0       0
[V.sub.6]       0       0.2     1.54    1.78
[V.sub.7]       0.3     0       0       0
[V.sub.8]       0       1.18    0.4     1.84
[V.sub.9]       0.86    0       0       0
[V.sub.10]      0       0.11    0.87    0.04
[V.sub.11]      1.96    0       0       0
[V.sub.12]      0       1.16    0.15    1.38
[V.sub.13]      1.86    0       0       0.01
[V.sub.l4]      0       0.63    1       0.02
[V.sub.l5]      1.49    0       0       0.01
[V.sub.l6]      0       0.81    0.15    1.43
[V.sub.l7]      1.13    0       0       0.01
[V.sub.l8]      0       1.6     0.4     0.08
[V.sub.l9]      1.1     0.01    0       0
[V.sub.20]      0       0.93    1.43    0.31
[V.sub.21]      1.89    0.06    0       0
[V.sub.22]      0       1.35    1.09    1.41
[V.sub.23]      1.01    0.19    0.01    0.01
[V.sub.24]      0       0.73    1.47    1.41
[V.sub.25]      0.07    0.58    0.05    0.01
[V.sub.26]      0       8.6     0.93    1.08
[V.sub.27]      1.06    1.27    0.19    0.02
[V.sub.28]      0       0.54    9.23    0.88
[V.sub.29]      1.05    1.84    0.58    0.06
[V.sub.30]      0       1.62    0.91    8.83
[V.sub.31]      11.22   1.21    1.27    0.2
[V.sub.32]      0       0.67    1.58    0.86
[V.sub.33]      1.04    0.77    1.85    0.58
[V.sub.34]      0       1.7     0.88    1.09
[V.sub.35]      1.09    1.29    1.21    1.27


(1) V. Karthikeyan and (2) V. Jamuna

(1) Assistant Professor, Electrical and Electronics Engineering (Marine), AMET University, Chennai - 603112, India.

(2) Professor, Electrical and Electronics Engineering, Jerusalem College of Engineering, Chennai - 600100, India.

Received 12 February 2015; accepted 20 March 2016; published 25 March 2016

Address For Correspondence:

V. Karthikeyan, AMET University, Department of Electrical and Electronics Engineering (Marine), 135, East Coast Road, Kanathur.Chennai. India. E-mail: vasu.karthi@gmail.com

Caption: Fig. 1: Functional block diagram of the RSRV-MLI

Caption: Fig. 2: Circuit diagram of 9-level RSRV-MLI

Caption: Fig. 3: Carrier and reference waveforms for the PDPWM of 9-level RSRV-MLI

Caption: Fig. 4: Functional block diagram of PDPWM for 9-level RSRV-MLI

Caption: Fig. 5: Simulation model of 9-level RSRV-MLI with PDPWM

Caption: Fig. 6: Gating pulses for (a) Polarity generator (b) Magnitude generator of 9-level RSRV-MLI with PDPWM

Caption: Fig. 7: (a) Output voltage (b) Output current waveforms of 9-level RSRV-MLI with R-load

Caption: Fig. 8: Harmonic spectrum of output voltage and current of 9-level RSRV-MLI with R-load

Caption: Fig. 9: (a) Output voltage (b) Output current waveforms of 9-level RSRV-MLI with RL-load

Caption: Fig. 10: Harmonic spectrum of (a) output voltage (b) output current of 9-level RSRV-MLI with RL-load

Caption: Fig. 11: Harmonic spectrum of PDPWM based 9-level RSRV-MLI for different even valued frequency modulation index

Caption: Fig. 12: Harmonic spectrum of PDPWM based 9-level RSRV-MLI for different odd valued frequency modulation index

Caption: Fig. 13: Harmonic spectrum of PDPWM based 9-level RSRV-MLI for different amplitude modulation index and [m.sub.f] =25
Table 1: Switching sequences of 9-level RSRV-MLI

Level   Output         Switching Functions
        Voltage                                Polarity
        (Van)          Magnitude               generator
                       Generator               ([S.sub.H1][S.sub.H2]
                       ([S.sub.a1][S.sub.b1]   [S.sub.H3][S.sub.H4])
                       [S.sub.a2][S.sub.b2])

1       4[V.sub.dc]    1010                    1100
2       3[V.sub.dc]    0110                    1100
3       2[V.sub.dc]    1001                    1100
4       [V.sub.dc]     0101                    1100
5       0              xxxx                    1010/0101
6       -[V.sub.dc]    0101                    0011
7       -2[V.sub.dc]   1001                    0011

8       -3[V.sub.dc]   0110                    0011
9       -4[V.sub.dc]   1010                    0011

Table 2: Simulation parameters of PDPWM based 9-level RSRV-MLI

Parameter                    Value

Number of levels             9
Number of sub-modules        2
Number of switches           8
Number of DC sources         3 (55 V, 55 V and 110V)
Modulation                   Phase Disposition PWM
Frequency Modulation Index   25
  ([m.sub.f])
Amplitude Modulation Index   1.0
  ([m.sub.a])
Fundamental frequency        50Hz
Load                         For R-load 1000H, For
                             RL-load 50 [ohm], 250mH

Table 3: Performance summary of 9-level RSRV-MLI with
PDPWM

Parameter                                   R-load   RL-load

Number of levels                            9        9
Number of switches                          8        8
Magnitude of fundamental voltage            219 V    218.8 V
Frequency modulation index                  25       25
Amplitude modulation index                  1.0      1.0
Fundamental frequency                       50 Hz    50 Hz
Magnitude of [V.sub.3] (% of fundamental)   2.19     2.2
Magnitude of [V.sub.5] (% of fundamental)   0.51     0.53
Magnitude of [V.sub.7] (% of fundamental)   1.12     1.08
Magnitude of [V.sub.9] (% of fundamental)   0.28     0.29
Voltage THD (in %)                          9.12     9.24
Current THD (in %)                          9.12     0.9
Distortion Factor (DF)                      0.0077   0.0077
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Author:Karthikeyan, V.; Jamuna, V.
Publication:Advances in Natural and Applied Sciences
Date:May 1, 2017
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