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Performing DS1 Signal Testing with a User-Configured Test Set.

This is the second article of a three-part series titled "DS1 Signal Tests with a User-Configured Test Set." The first part, subtitled "Testing Today" and published in November CN, covered conventional DS1 signal framing, relevant DS1 signal tests, and the relationship between the DS1 signal and the T1-carrier system. This article is subtitled "Testing Tomorrow" and covers the extended superframe, bipolar eight-zero substitution, and other aspects of DS1 signals that will be encountered in the near future. Tests appropriate for the coming DS1 signal are described. The last part, subtitled "Testing After Tomorrow," will cover the testing of DS1 signals in new applications that are evolving.

The theme of this series of articles is that assorted test functions for both today's and tomorrow's DS1 signal can be selected and combined by a user into an instrument that meets his particular needs. The preceding article described today's DS1 signal and test functions consistent with such a user-configured test set; this article describes tomorrow's.

To quote an inscription found on a telephone pole that has since disappeared: "The good news--everything ends; the bad news--everything ends." This applies to telephone companies as well as life. Although the old American Telephone and Telegraph Company has ended, its influence has not. DS1 signal testing tomorrow will certanily reflect developments begun in that system and sustained by its divested components. Although it's not possible to predict all of the concepts that will be carried forward into general use by technological inertia, the extended superframe format (ESF) and bipolar eight-zero substitution (B8ZS) are two likely candidates.

In early 1981, the extended superframe format, then called the extended framing format, was publicly declared the Bell System's new standard framing format for all new designs of DS1-level equipment that frame on the 193rd bit position in the frame of the 1.544-Mb/s DS1 signal. Extensive use of equipment using the ESF format is imminent.

While robbed-bit signaling imposed an imperceptible distortion when the least-significant bit in each of the 24 DS0 channels of every sixth frame was stolen for a signaling indicator, the ESF format imposes no penalty except that more frames must be examined before synchronization can be established. Because the framing techniques that are practical using today's technology are so much faster than those used with the pre-ESF formats, even the stretched distributed framing pattern usually won't result in more time spent searching for frame. ESF Format Adds Features

Besides providing the 24 DS0 channels in each frame that pre-ESF formats did, the ESF format adds these features:

* A 4-kb/s data link that can be used for maintenance information, protection switching, supervisory signaling, or practically any other purpose.

* A six-bit cyclic-redundancy-check code, CRC-6, included with each frame and generated from the bits of the preceding frame (after all framing bit positions of that frame are set to 1). The check character can be used for transmission performance monitoring, false-framing protection, or any other purpose for which a measure of DS1 signal quality is required.

* Two additional robbed signaling bits--"C" and "D"--added to the "A" and "B" signaling bits in pre-ESF formats allow up to 16 signaling states to be represented. Format options are available for transparency (no robbed signaling bits), two-state signaling (A-bit only), four-state signaling (A and B bits only) or 16-state signaling (with A, B, C and D bits robbed).

Figure 1 shows how the ESF format for DS1 signals adds the preceding features to the pre-ESF format without decreasing DS0 channel capacity or increasing the 1.544-Mb/s bit rate.

The top row in Figure 1 shows the contents of successive framing bit positions for a DS1 signal in the pre-ESF format (192 bits for the 24 DS0 channels in each frame are, of course, between framing bits but are not shown in the figure). Recall that the pattern repeats every 12 frames ("superframe" for this format) and that the framing bit position occurs at a rate of 8,000 times per second (because there are 8,000 frames per second). D Denotes a Data Link Bit

The bottom row in Figure 1 shows the contents of successive framing bit positions for a DS1 signal in the ESF format (again, with 192 bits for 24 DS0 channels between framing bits). "D" in a position denotes a data link bit in that framing bit position. "C" denotes a CRC-6 bit in that position. Either "0" or "1" denotes a framing bit position with the value shown.

Note that the framing bit position sequence repeats after 24 frames (extended superframe) instead of 12 (superframe) even though there are only six bits in the framing pattern instead of twelve. The consequence of this is that at least 24 frames instead of 12 have to be examined for the framing pattern, which is why framing, at least theoretically, takes longer for the ESF format.

Because there are only six framing bits per 24 framing bit positions in the ESF format, the framing bit occurs at a 2-kb/s rate even though the framing bit position occurs 8,000 times per second. Because a data link bit occupies every other framing bit position, it occurs at a rate of 4,000 bits per second. Like the framing bit, the CRC-6 bit uses every fourth framing bit position and occurs at a 2-kb/s rate.

The preceding paragraphs presented a global view of the ESF format. The following describes some ESF details that were proposed for what used to be the Bell System's use and that will be implemented in equipment initially by the Bell System's heirs and ultimately (probably) by nearly everyone else.

What does the data link look like if the data link feature isn't implemented? The prescription is all "ones," except if a terminal is receiving a DS1 signal for which it cannot find frame. Then it uses the data link (even though it's nominally not implemented) to continuously transmit a pattern of eight ones followed by eight zeros to the sending terminal. This "yellow alarm" tells the sending terminal that the receiving terminal cannot frame on the sending terminal's signal.

Robbed-bit signaling occurs in every sixth frame of the 24-frame ESF. (In the transparent signaling option, all eight bits of all channels in all frames are used for traffic.) When only the A signaling bit is used, the least-significant bit of every sixthf frame shows A-bit signaling. When both the A and B signaling bits are used, the first and third signaling frames of the ESF show A-bit signaling and the second and fourth signaling frames of the ESF show B-bit signaling. When A, B, C, and D signaling bits are used, they occur in the ESF's first, second, third and fourth signaling frames, respectively.

The CRC-6 code prescribed for ESF is able to detect 98.4 percent of ESF's containing one or more transmission errors. Especially because there are only six bits in the ESF framing pattern, the CRC-6 code can be useful in providing false-framing protection. Naturally, there are occasions when the framing pattern sequence occurs in a bit position other than in the framing bit position. Framing Seems to Go In and Out

In fact, a framing-pattern-sequence detector monitoring a DS1 signal stream consisting of a random sequence of bits will continually appear to go in and out of frame. This presents no problem provided the detector realizes that it hasn't found frame (for example, when two out of the next four bits in the assumed framing bit position aren't in the expected sequence).

Then it will resume the search.

However, a serious problem can arise when a signal in a channel mimics the framing pattern in one of its bit positions (a condition especially likely where DS0 channels carry data). Equipment that finds that position may lock on it, declaring frame although not actually synchronized. However, the CRC-6 code in the ESF format will continually exhibit errors for this condition, so that the need to continue the search for frame will be apparent. The pre-ESF format did not provide this mechanism for protection against false framing.

The restrictions that the DS1 signal should have no more than 15 consecutive zeros and have at least 12.5-percent average ones density are imposed by circuits that receive the signal and extract the inherent 1.544-megahertz clock from it. (Remember that 1 is a positive pulse or negative pulse and 0 is no pulse.) Even if the restrictions could be relaxed by using other circuit techniques and recent technology in new terminal equipment, the enormus installed base of T1-carrier transmission facilities would keep the restrictions intact. Fiber-Optic Comes into Play

Tomorrow's DS1 signals will, therefore, continue to be carried by today's repeatered T1-carrier transmission facilities. (After tomorrow, fiber-optic transmission facilities will change this, and the DS1 signal will probably appear only as a multiplexer input, demultiplexer output, or a signal buried within the interface to a digital switch.)

The consecutive-zeros-and-ones density restrictions were tolerable when the digital signal transmitted was encoded voice and the arbitrary insertion of a 1 in the least-significant bit position of an all-zero-encoded sample couldn't be detected by the listening ear. Even when the received encoded sample was for a tone representing digital data emanating from a modern, the receiving modem was not affected by the arbitrary insertion of a 1 in the least-significant bit position of an all-zero sample. However, when the bits in a channel of a DS1 signal represent bits of data--as in the Digital Data System (DDS) and other applications--instead of bits for an encoded analog signal sample, it's no longer possible to be casual about substituting ones for zeros.

This problem was solved in DDS by providing a "network control bit" in every frame for each digital data channel. The network control bit is always 1 when customer data is being sent in that channel so that the customer can send as many consecutive zeros as wanted and the average ones density in that channel will be no less than one in eight no matter what the customer sends. Because every digital data channel has the network control bit and every channel with an encoded analog signal has no all-zero sample, the restrictions are met by each channel and, therefore, by the DS1 signal stream.

Furthermore, when customer data is not being sent in DDS, the network control bit is always 0 and a code, asssigned so that at least one of its bits is 1, is being sent in that channel. Although this technique overcomes the restrictions on consecutive-zeros-and-ones density, the maximum rate for customer data in the channel is limited to 56 kb/s (8,000 frames per second times seven customer data bits per frame) instead of the 64 kb/s that the channel is capable of. Wants Clear-Channel Capacity

In early 1981, the Bell System publicly declared that all new DS1 equipment made for them must include "clear-channel capability," that is, the ability to transmit a DS0 or DS1 signal unconstrained by a ones-density or number-of-consecutive-zeros restriction. The prescribed implementation was "bipolar with eight-zero substitution" coding of the DS1 signal. Figure 2 illustrates B8ZS.

At the top of the figure is a series of zeros and ones that represent the values of successive bits in the DS1 signal stream. Below that is a schematic representation of the bipolar bit stream without B8ZS for the bit values in the top row. At the bottom of the figure is a schematic representation of the bipolar bit stream with B8ZS for the same bit values. Figure 2(a) shows the B8ZS implementation when the 1 preceding the eight zeros is represented by a positive pulse in the bipolar DS1 signal stream. Figure 2(b) shows the B8ZS implementation when the preceding 1 is represented by a negative pulse.

In each case, two bipolar violations (occurrences of successive pulses that have the same polarity) are deliberately inserted in place of a string of eight zeros. Normally, bipolar violations are a sign of trouble and used as a measure fo diminished transmission quality. However, when they occur in this predetermined pattern, they indicate eight successive zeros in the DS1 stream. Note that as many positive pulses as negative pulses are inserted so that no DC component is added. Whether Equipment Accepts B8ZS

Equipment capable of accepting B8ZS can be used with a DS1 signal source whether or not the source incorporates B8ZS. However, a signal source incorporating B8ZS can only be used with receiving equipment capable of accepting B8ZS.

Most of the test functions appropriate for tomorrow's DS1 signal are analagous to test functions performed for today's DS1 signal except that they reflect the enhancements provided by the ESF format and accommodate the clear-channel capability provided by B8ZS.

Test functions performed by available modules include ESF channel access, ESF data link access, ESF signaling display and ESF CRC-6 error accumulation. A module that bridges the transition between the pre-ESF and the ESF DS1-signal formats was described in Part 1 of this series (see Figure 3 here). The module shows whether the format of a DS1 singal being monitored is standard (pre-ESF) or ESF. It also shows whether or not the monitored DS1 signal incorporates B8ZS.

One additional DS1-signal test function needs comment, even though it applies as much to today's DS1 signal as it does to tomorrow's. The DS1 signal is a constitutent of the other signals in the digital hierarchy. For example, there are two DS1 signals in the DS1C signal at 3.152 Mb/s and four DS1 signals in the DS2 signal at 6.312 Mb/s. Tests on the DS1 component can be used to infer which part of the facilities serving a higher signal rate may be impairing performance. Therefore, extraction of the DS1 signal from other signals in the digital hierarchy is a function that allows all the other DS1-signal test functions to be performed so that inferences can be drawn for the facilities serving the higher signal rate. Module Performs These Functions

Any one of the 24 channels in an ESF-format DS1 signal stream can be selected so that all four of its signaling bits are displayed (A, B, C and D) and so that the decoded VF for that channel is accessible for input to a transmission measuring set or speaker driver. These functions are performed by the Extended Framing Channel Access Module (Figure 4).

For an ESF-format DS1 signal in an application that uses the transparent signaling option, the signaling bit display is meaningless. In the two-state signaling option, all four display positions will be identical and show the A-bit. In the four-state signaling option, the A and B-bit display positions will show the A and B bits, respectively, and the C and D-bit display positions will do the same. In the 16-state signaling option, the A, B, C and D-bit display positions will show the state (0 or 1) of the A, B, C and D bits, respectively.

All of the tests described for the channel access function in the first article of this series apply equally well to a DS1 signal in the ESF format.

An important function of tomorrow's DS1 signal tests will be extraction of the data link. The major benefit of the ESF format is the addition of a 4-kb/S data channel to the DS1 signal without any impairment in the twenty-four 64-kb/s DS0 channels.

Protocol for the data link in the ESF format is not part of the format specification so that any protocol suitable to an application can be used. However, it is expected that, at least in some applications, Link Layer (Level 2) protocol compatible with CCITT Recommendation X.25 will be used. When that protocol is used, a count of frame-checking-sequences (FCS) errors is a useful test function because it provides a measure of performance for the facilities associated with the data link. Unit EXtracts Data Link

Extraction of the data link and, when appropriate, accumulation of an FCS error count are performed by the Extended Framing Data Link Module shown in Figure 5. The data link is presented in the form of a data signal and an associated 4-kHz clock signal. The FCS error count is accumulated in a four-decimal-digit counter and the accumulated count is displayed on the front panel. The front-panel display also shows when the data link is not implemented or when a yellow alarm is being received, which means that the remote terminal is not able to synchronize on the DS1 signal that it receives from this terminal. A front-panel push-button allows the user to clear the FCS error count.

The state of the A, B, C and D signaling bits for all 24 channels of a DS1 signal in ESF format can be observed at one time. This function is valuable for determing traffic on a facility on which a service interruption may be contemplated or for verifying signaling performance of channel units.

The function is performed by the Extended Framing Signaling Display Module shown in Figure 6. A, B, C and D signaling bit states are indicated by four light-emitting diodes (LEDs) for each channel. Each Displays Signaling State

The LED is on when the associated signaling bit is one, and off when the signaling bit is zero. Because all 24 channels display their signaling states, 24 sets of four LEDs appear on the module's front panel, making the signaling states of all 24 channels quickly apparent.

Cyclic-redundancy-check (CRC) codes are a powerful category of parity check codes. The advantages of CRC codes are simple implementation, effective random-error detection for a given level of redundancy, and the ability to be tailored to known burst-error characteristics. The essential quality of a cyclic code is that any cyclic permutation or end-around shift of a code word results in another code word.

The CRC-6 code used in the ESF format provides six redundant check bits in each ESF. The check bits in an ESF are generated from all the bits of the preceding ESF after the framing bits in that ESF have all been made 1. If the six check bits generated for an ESF by a receiving circuit do not agree with the six check bits in the next ESF received, a transmission error is indicated. CRC-6 Provides Integrity Check

In Part 1 of this series, framing bit errors were counted and used as an index to the quality of the remainder of the transmission. Because CRC-6 check bits are generated using all the information bits in the ESF, it provides an even more powerful check on the integrity of transmission. However, when the bit error rate is high, observing the framing-bit-error count is easier than observing the CRC-6 error count, for in the former case a million bits being monitored for error take 125 seconds because only framing bits are being checked, but in the latter case they take less than a second because all bit except the framing bits are being checked.

The CRC-6 error-accumulating function is performed by the Extended Framing Error Accumulating Module shown in Figure 7. A four-decimal-digit counter accumulates CRC-6 errors and the module continuously displays the counter's contents when the unit is powered and in frame. A pushbutton allows the user to clear the counter.
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Copyright 1984 Gale, Cengage Learning. All rights reserved.

Article Details
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Author:Fryer, W.
Publication:Communications News
Date:Dec 1, 1984
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