# PLL as the frequency synthesizer with continuous phase divider/Fazine kilpa naudojantis daznio sintezatorius su tolygiuoju fazes dalikliu.

PLL synthesizerThe PLL (Phase Locked Loops), as it is well known [1], could be used on two ways, depending on whether the output is an error voltage, which is used for regulation of the voltage controlled oscillator (VCO), or the output is the signal itself (voltage) generated by the VCO. In the first case, it has been used for FM signal detection [2], since the error voltage has the shape of the modulating signal. The second important usage of the PLL, in frequency synthesis, has been enabled by the fact that frequency of the signal generated by the VCO is equal to the frequency of the referential signal, and its phase shift is clearly defined in relation to the phase shift of the referential signal. This kind of synthesizers with usage of just one quartz crystal and programmable (frequency) divider enables (practical) realization of highly stable frequencies [3] within a given frequency range, with the given frequency raster or step. They have been used in realization of highly stable generators of carrying frequencies at transmitters, as well as in local oscillators in radio and TV receivers.

The mostly used PLL in frequency synthesis is given in Fig.1. It consists of the following fundamental components (pieces): phase detector (FD), loop filter (NF), voltage controlled oscillator (VCO), and frequency divider (N).Afterwards the circuit synchronization the following condition is fulfilled [f.sub.r] = [f.sub.in], therefore the synthesizer output frequency is

[f.sub.out] = [Nf.sub.in]. (1)

If variation of [f.sub.out] is required within a given range, then the dividing factor in the feedback branch N of the PLL circuit has to be changed from [N.sub.min] to [N.sub.max]. Although the PLL synthesizer either with variable or constant dividing module is one of the mostly used synthesizers, it has a serious disadvantage. Namely, in order to create a period of the divider's output signal, which together with referential signal in FD creates the error voltage, it is necessary n VCO periods to elapse, which means that during all this time the VCO is out of control.

[FIGURE 1 OMITTED]

A solution that resolves this disadvantage is usage of look-up tables, Fig. 2.

[FIGURE 2 OMITTED]

As stated, the continuous phase divider considered here is based on look-up table. Suppose that the range of required frequencies is from [f.sub.min] to [f.sub.max], where

[f.sub.min] = [N.sub.min] [f.sub.ref], [f.sub.max] = [N.sub.max] [f.sub.ref]. (2)

The look-up tables, Fig.2. store [N.sub.max] - [N.sub.min] vectors of numbers, where each vector belongs to one of the required frequencies. The length of vector which belongs to the frequency f = [Nf.sub.ref] is

n = N/p (p = 1,2, ..., N/2) (3)

and it contains m samples of one period of the reference signal. After m periods of the VCO, the process is repeated, and thus the phase of the VCO is divided almost continuously by N . Obviously, for the case when p = 1 (n N) , the obtained approximation is the best one.

A typical solution for resolving this problem is usage of look-in tables [4], in which are memorized samples of the sinusoidal function with n discrete values, while the number of discrete values is equal to the wanted module of the divider. One discrete value is read from the memory in every VCO period, afterwards it is sent to the D/A converter and then to the phase detector where together with referential voltage gives the regulating (control) voltage influencing VCO [4]. Subsequently, loop reaches the stable state faster (for less period of time), and it remains under control of the phase detector all the time by the end of the stable state.

In this paper, a hardware solution for generating sinusoidal function in samples instead of the look-in tables and D/A converters is proposed [5], on this way all advantages of the synthesis given in [4] are kept (preserved). The proposed solution is suitable for integration, resulting in the new integrated PLL synthesizer.

Realization of the divider as a sinusoidal waveform generator

The operational amplifier gain as well as the descrete sinusoidal function, i.e. sin(2[pi][f.sub.0][DELTA]tk), are regulated by resistors [2], where k is the serial number of the sample within a VCO period, and [DELTA]t is duration of a sample. Variable gain of the operational amplifier is attained by a set of resistors, whereby only one of the resistors is switched on in the circuit at a moment of time, and stays switched on for the period of time [DELTA]t. The resistors are switched on by a switch (chopper), and their operation is controlled by the control logic

[u.sub.2](t) = A sin(2[pi][f.sub.0]t)[U.sub.i]. (4)

Discretization of this function is performed on the way that k[DELTA]t is introduced instead of t, where k is the serial number of the sample, on that way the signal in the descrete number of points is obtained i.e.

[u.sub.2](t) = A sin k[DELTA][theta][U.sub.1], (5)

where

[DELTA[theta] = 2[pi][f.sub.0][DELTA]t = 1/[nf.sub.0]. (5)

Realization of (5) could be performed by the circuit given in Fig. 3. The output signal of this circuit is

[U.sub.2] = [AU.sub.1] = R/[R.sub.k] [U.sub.1], k = 1,2 ... n. (6)

If we suppose that [U.sub.1] is a constant voltage equal to one ([U.sub.1] = 1), then

[U.sub.2] = R/[R.sub.k], k = 1,2 ... n, (7)

where [R.sub.k] is the serial number of the resistor which is switched on in the curcuit. The negative half-period of the sinusoudal function is achived by an AND circuit, i.e. by the input signal of the opposite polarity.

[FIGURE 3 OMITTED]

Values of the resistors [R.sub.k] from the previous expressions are:

[R.sub.k] = R/sin(k[DELTA][theta]), k = 1,2 ... n, (8)

where [DELTA[[theta] = 360[degrees]/n and n - the number of points in which

discretization of the function is performed. In Table 1 value "1" means that the resistor is switched on, while "0" means that the resistor is switched off.

The new PLL synthesizer

The new PLL frequency synthesizer with the continuous phase divider is shown in Fig. 4. The output signal from the voltage controlled oscillator is used for triggering of the sinusoidal waveform generator in which n samples of the sinusoidal waveform are actually generated, whereby n is the number of discrete points equal to the dividing module. By this realization, one sampled value of the sinusoidal function is generated within every VCO period and sent to the phase detector. This allows presence of the both signals in the phase detector starting from the first VCO oscillation period, which subsequently causes faster reaching of the stable state. Additionally, the system is permanently controlled by the voltage from the phase detector.

[FIGURE 4 OMITTED]

In the real implementation, variation of the operational amplifier gain has to be realized by progressive turning switches (choppers) on from the first one to the last one. In Table 2. are given values for [[theta].sub.k], and sin [[theta].sub.k], as well as values of the resistors needed for generating of the resistor network output signal, based on samples, in the case that discretization of the sinusoidal function is performed in 24 points, which subsequently means n 24 and [DELTA][theta] = 15[degrees].

By (9), and for R = 10k[OMEGA], value of the resitor [R.sub.k] is calculated. That resistor is turned on in the circuit within the period of time [DELTA]t and refers to the k - th sample of the discretized sinusoidal function. On this way, discrete values of the sinusoidal function are realized for a quarter of the half-period (0 - [pi]/2). For the second quarter of the half-period ([pi]/2 - [pi]) the switches has to be progressively turned off from the last one to the first one. The negative half-period is realized by repeating the previous procedure with turning the switch S12 on, whereby the input DC voltage [U.sub.1] is now inverted, i.e. negative. This procedure reduces glitch magnitudes in the waveform of the output signal comparing to the solution where a certain discrete value of the sinusoidal function is realized by one resistor only, and the next value by switching-off that one and switching-on some other resistor (Table 1).

For the proposed practical implementation, discretization of the sinusoidal function is performed in 24 points, and in the table we don't start with " 0[degrees]", but with "[theta]/2" in order to avoid generation of the value " sin 0[degrees]" for which [R.sub.e] has an infinity value. In order to accomplish progressive turning switch on, [R.sub.e](k) represents resistors arranged in a parallel connection assigning the appropriate discrete value of the voltage [U.sub.2] to k - th sample, whereby that value is calculated by (9). If R = 10k[OMEGA], then from [R.sub.e] it follows: [R.sub.1] = 76,9f[OMEGA] [R.sub.2] = 39,5f [OMEGA], [R.sub.3] = 44,4f[OMEGA], [R.sub.4] = 54,05k[OMEGA], [R.sub.5] = 76,3f[OMEGA] and [R.sub.6] = 149,25k[OMEGA].

[FIGURE 5 OMITTED]

The control logic from the Fig. 5 consists of counter CNT, read only memory ROM, and flip-flop FF. State of the counter is defined by equidistant phase shift from the Table 2. The sinusoidal signal has been generated in two half-periods. Within the first half-period, 0-180[degrees], the switch SW is in the position "1", while in the second one 180[degrees]-360[degrees], the switch SW is in the position "0". State of the switch SW is controled by flip-flop FF, which is induced by the signal from the line with highest weight of the counter CNT. The analog switch [S.sub.1] is continuously turned on while lines from [O.sub.1] to [O.sub.5] regulate switches from [S.sub.2] to [S.sub.6].

Conclusion

In this paper a new method for frequency synthesis based on the PLL with continuous phase divider has been presented. Look-in table and the D/A converter are replaced by the generator in which n samples of the sinusoidal wave form are generated. The number of the discrete points is eqaul to the modulus of the divider. On this way, a new realization of the dividing function with continuous phase has been enabled. This method of frequency synthesis is characterized by short period of time necessary for reaching the stable state and high purity of the output frequency.

References

[1.] Best R. Phase-Locked-Loops.--Desing and Applications, New York: McGraw-Hill, 1993.

[2.] Krstic D., Raicevic A. On a Frequencu Response of PLL FM Demodulators in the Presence of FM Signals // Facta Universitatis, Series: Electronics and Energetics, University of Nis, Serbia.--1995.--Vol. 8, No. 2.--P. 211-223.

[3.] Heung-Gyoon Ryu, Hyun-Seok Lee. Analysis and minimization of phase noise of the digital hybrid PLL frequency synthesizer // IEEE Transactions on Consumer Electronics.--2002.--Vol. 48, No. 2.--P. 304-312.

[4.] Wulich D., Bar M and Kost O. Fast frequencu synthesizer based on PLL and a continuonis phase divider // Int. J. Elektronics.--1991.--Vol. 70, No. 5.--P. 891-899.

[5.] Krstic D., Petrovic B., Jovanovic G. Novi digitalni FM stereo koder matricnog tipa // Telsiks.--Nis, Serbia.--1999.--P. 143-146.

A. M. Raicevic

The Faculty of Technical Sciences, University of Pristina, Kneza Milosa 7, 38220 Kosovska Mitrovica, Serbia, phone: +381 28 425320; e-mail: andjraic@eunet.rs

B. M. Popovic

Academy of Criminalistic and Police Studies, Cara Dusana 196, 11080 Belgrade, Serbia, phone: +381 11 3161444, e-mail: cica@ptt.rs

Table 1. Values of resistors [[theta].sub.k][0] Sin[[theta].sub.k] [R.sub.k][k[OMEGA]] [R.sub.1] 7.5 0.130 76.923 1 22.5 0.383 26.110 0 37.5 0.608 16.447 0 52.5 0.793 12.610 0 67.5 0.924 10.882 0 82.5 0.991 10.091 0 97.5 0.991 10.091 0 112.5 0.793 10.822 0 127.5 0.793 12.610 0 142.5 0.608 16.447 0 157.5 0.383 26.110 0 172.5 0.130 76.923 1 [R.sub.2] [R.sub.3] [R.sub.4] [R.sub.5] [R.sub.6] 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 Table 2. Values of resistors [[theta].sub.k][0] Sin[[theta].sub.k] [R.sub.k][k[OMEGA]] [R.sub.1] 7.5 0.130 76.923 1 22.5 0.383 26.110 1 37.5 0.608 16.447 1 52.5 0.793 12.610 1 67.5 0.924 10.882 1 82.5 0.991 10.091 1 97.5 0.991 10.091 1 112.5 0.793 10.822 1 127.5 0.793 12.610 1 142.5 0.608 16.447 1 157.5 0.383 26.110 1 172.5 0.130 76.923 1 [R.sub.2] [R.sub.3] [R.sub.4] [R.sub.5] [R.sub.6] 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0

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Title Annotation: | ELECTRONICS/ELEKTRONIKA; phase locked loop |
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Author: | Raicevic, A.M.; Popovic, B.M. |

Publication: | Elektronika ir Elektrotechnika |

Article Type: | Report |

Date: | Jun 1, 2009 |

Words: | 2344 |

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