PCB stackup analysis and design, part 3: PCB material selection requires the evaluation of electrical, mechanical and thermal properties, as well as price.
FIGURE 8 exemplifies impedance computation for a coplanar differential pair.
The parameters comprise trace width = 12 mil, trace thickness = 2 mil, dielectric thickness = 8 mil, dielectric constant = 3.38, intrapair separation = 15 mil, line to ground clearance (horizontal) = 10 mil, solder mask thickness = 0.8 mil and solder mask dielectric constant = 4.5. Si8000 predicts differential impedance of 100.43 [omega]. This denotes a nominal calculation, but frequently it is necessary to consider impedance tolerances.
A typical tolerance value is +/- 10%. A differential impedance of 100 +/- 10% implies variation from 90 [omega] to 110 [omega]. Sometimes, it is desirable to have a tighter tolerance such as +/- 5%, since impedance tolerance often involves trade-off between impedance of PCB traces, package, driver output impedance and termination resistors. Tightening the PCB trace tolerance makes it feasible to relax the constraints on other parameters (package, driver, termination), but this also increases board fabrication cost. A 5% tolerance is more expensive to manufacture than a 10% tolerance, which is costlier than a 15% tolerance. (25)
Three main materials (3) in a multilayer PCB embrace copper foil sheets, resin and woven glass cloth. Cores or laminate sheets are constructed by affixing copper foil to one or both sides of fully cured prepreg sheets. Prepreg mats are a weave of glass fiber yarns preimpreganted (28) with partially cured resin.
Several resin types are utilized for prepreg preparation. These resin systems usually differ in electrical properties (such as dielectric constant and loss tangent) and mechanical/thermal characteristics (coefficient of expansion, glass transition temperature and rate of moisture absorption).
The commonly used FR-4 has a woven glass/epoxy resin composition.
However, there are alternatives such as GETEK, MEGTRON, BT, polyamide (28) and cyanate resin material, with attractive mechanical or electrical properties (low dielectric constant and loss tangent).
Fibers are applied to strengthen the resins; these comprise the electrical grade E glass and structural grade S glass. E glass is more common, but S glass is stronger and has lower Er (also more expensive) than E glass. Addition of fiber to resin alters the electrical and mechanical characteristics of the composite structure based on glass-to-resin ratio. FR-6 utilizes a polyester (29) resin system plus glass matte reinforcement and is suitable for flame resistant (30), low capacitance or high impact applications.
Solder mask / resist is a coating that protects PCB traces and prevents solder bridges and shorts. It facilitates wave soldering applied in mass assembly. Solder mask is a lacquer-like polymer layer often applied with a green tint, but it is available in various colors and finishes. A common solder mask (31) is Liquid Photo Imagable (LPI).
For a multilayer PCB, the copper thickness does not have to be the same for all stackup layers. It is also unnecessary for all the cores to be of the same laminate. Hybrid-type construction has been gaining popularity. The PCB conductor and dielectric losses (32) constitute another critical consideration.
The DC conductor resistance is governed by Equation 5 All of the Equations can be found in FIGURE 9. Here, [R.sub.dc] represents resistance per unit length for DC currents, p is the bulk conductor resistivity (33) W is trace width and t is thickness. The conductor DC losses are directly related to [R.sub.dc] and are frequency independent.
DC losses are negligible for short traces of large cross sections and become important for long lines of small cross-sectional geometries and for multi-drop topologies. In Equation 6, [R.sub.ac] symbolizes the AC conductor resistance per unit length and [??] is the skin depth. [R.sub.ac] can be reduced by widening the trace width. It varies inversely with [??] and directly with [square root of f]. When ascertaining the total AC resistance, it is necessary to also account for resistance of return current on the reference plane. Furthermore, the conductor AC loss is directly related to [R.sub.ac] and hence proportional with the square root of frequency.
[FIGURE 8 OMITTED]
Equation 7 is a skin depth expression with [sigma] being the conductor's conductivity (inverse of resistivity [rho]), [[mu].sub.0] is permeability of free space, pr is conductor's relative permeability and f is sine-wave frequency. When f is in Hz, [sigma] in Siemens/meter and 9 [[mu].sub.0] in Henries/meter (4[pi]E-7), then Equation 7 produces [??] in meter. Equation 8 is a simplified skin depth formula (34) applicable to copper ([sigma] = 5.6E7 Siemens/m and [mu]r=1), with [f.sub.mhz] being frequency in MHz and [[delta].sub.cu] in micron.
In Equation [9[[alpha].sub.diel] represents attenuation associated with dielectric loss (32) in dB/in, [f.sub.ghz] is frequency in GHz and Er is substrate dielectric constant.
FIGURE 10 presents dielectric loss--[[alpha].sub.diel] (based on Equation 9) for several materials, generated with the aid of Mathcad. The curve RO4 (Rogers 4350) displays the least and FR-6 the most attenuation in this comparison.
NeS (Nelco N4000-13SI), which utilizes S glass, is less lossy than NeE (Nelco N4000-6 Hi Tg FR4), based on E glass.
At high frequencies, for typical PCB trace dimensions, the dielectric losses being proportional to frequency can become dominant (32) over conductor DC losses (frequency independent) and AC losses (proportional to [square root of f]).
In addition to conductor and dielectric losses, the effects due to roughness of conductor surface can be significant. Conductor roughness is often expressed as tooth structure (14) and the amount of surface variations is portrayed as tooth size. Conductor surface roughness can effectively increase the material resistance when the mean surface roughness is a significant percentage of skin depth. For instance, at a frequency of ~ 200 MHz, the skin depth of copper is 4.667 micron, which approximately equals the typical PCB surface roughness (~ 4 microns to 7 micron). Frequency harmonics exceeding 200 MHz will then deviate from the ideal loss formulae (14). For producing low loss interconnects, it is desirable to have smooth copper foils.
[FIGURE 9 OMITTED]
[FIGURE 10 OMITTED]
When selecting PCB materials, some parameters that need to be considered include the conductor and dielectric losses, the electrical characteristics, the mechanical/thermal properties and the price.
There are other important contemplations involved when ascertaining optimum materials for PCB stackup, such as impact of glass weave (35) in PCB laminates on Gigabit per second signals and also meeting standards (IPC specifications). These will be discussed in Part 4 of this article.
Editor's Note: References 1-25 can be found in Parts 1 and 2 of the series.
(26.) Gary Melchior, "LMH0034 PCB Layout Techniques," National Semiconductor Application Note 1372, July 2006.
(27.) Eric Bogatin, "Board Stackup's Important Tool," Printed Circuit Design & Manufacture, December 2003, pgs. 18-20.
(28.) Stephen C. Thierauf, "High-Speed Circuit Board Signal Integrity," Artech House, Inc., 2004, pgs. 2-9.
(29.) Clyde E Coombs, Jr., "Printed Circuits Handbook, Fifth Edition," McGraw Hill Handbooks, 2007, Chapter 5.
(30.) Helen Holder, "Introduction to Surface Mount Technology," April 2002.
(31.) Al Williams, "Build Your Own Printed Circuit Board," McGraw-Hill, 2004, p. 14, p. 168.
(32.) Abe Riazi, "Engineer's rule of thumb simplifies PCB signal integrity" EE Design, August 19, 2002.
(33.) "Calculating Track Resistance;' Polar Instruments Ltd., Application Note AP144.
(34.) Abe Riazi, "Maxwell's Influence on Signal Integrity;' Printed Circuit Design & Fab, December 2007.
(35.) "PCB Dielectric Material Selection and Fiber Weave Effect on High-speed Channel Routing," Altera Corporation, AN-528-1.0, May 2008.
DR. ABE (ABBAS) RIAZI is a senior staff scientist hardware development with Broadcom Corporation in Irvine, California. He can be reached at firstname.lastname@example.org.
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|Title Annotation:||INTERCONNECT STRATEGIES|
|Author:||Riazi, Abe "Abbas"|
|Publication:||Printed Circuit Design & Fab|
|Date:||Feb 1, 2009|
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