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PAELib: A VHDL Library for Area and Power Dissipation Estimation of CMOS Logic Circuits.


Power estimation in early design stages of VLSI circuits is a must for the low-power applications of current day: mobiles, handheld devices and battery powered gadgets [1]. Beside power estimation, area estimation is important too, as thermal modeling makes use of these two quantities [2]. Power estimation could be carried out at each abstraction level by different tools: Spice simulators may be used at the transistor level; gate level power simulators are used to estimate power consumption - PowerPro RTL, XPE/XPA [3]; system profiling is often employed to estimate power dissipation at system level [4]. Often, these commercial tools are not available for a designer, but event-based logic simulators, such as ModelSim, Active HDL, Xsim, Ghdl, Icarus, supporting either Verilog [5] or VHDL [6] are. Thus, the idea of using an event-based simulator, instead of a power simulator, for power estimation is born.

The particular problem in power estimation of CMOS logic is that power dissipation depends on switching activity in the circuit (depends on the application and work frequency). Power estimation at the gate level can be carried out by static and dynamic methods [7]. While static methods make use of probabilistic information of the input stimuli to estimate switching activity in a circuit, dynamic ones use logic simulations to gather information about switching activity. Such a power estimation method was implemented in [8]. The shortcoming of the method is that it neglects the static power dissipation (due to subthreshold leakage in CMOS transistors) and does not account for power dissipation caused by incomplete logic transitions (glitches). In ref [9] a similar VHDL power estimation method is presented. This approach considers the input slope, output capacitive loading and glitches in the modeling of power/energy consumption. Another VHDL power simulator is presented in [10], where glitching power estimation is achieved by modifying the VHDL event handling and propagating ramps instead of infinite slope events. Of course, the above two solutions have their limitations: in an early design phase (i.e. register transfer level description), the layout of the circuit is unknown, hence parasitic effects (fin-in, fan-out, parasitic capacities of the wiring, delays between gates, etc) are unknown, thus estimation accuracy is easily compromised.

Beside power estimation, the occupied area is an important indicator for the designer. For example, a circuit could be implemented in several ways (i.e. a finite state machine could be one hot, binary or Grey encoded [11]) but the occupied area and power can be estimated after circuit synthesis only. Another example, where both power and area estimates are relevant, is the evaluation of power optimization methods, such as clock gating, precomputation and partitioning [12]; these methods come with a circuit overhead, thus in early design stages the designer must have an information about the power saving potential vs. area overhead of an optimization method.

Area estimation can be also carried out in a logic simulator if the number of gates and their area in its structural description are accounted. The area estimation is straightforward: the area of leaf components--such as logic gates, multiplexers, encoders, flip flops--are held in a lookup table and let the HDL code sum up the area of each leaf component. An area estimation methodology is presented in [13], where the RTL level VHDL description of the logic circuit is parsed, instructions are mapped to equivalent circuits and total area is obtained by adding all individual area of them.

In this paper, a joint power dissipation and occupied area estimation methodology in VHDL is given. PAELib is an extension of an earlier developed library PELib [14] that was deployed for static and dynamic power consumption estimation only. Currently, PAELib models off-the-shelf logic components from the well know 74 and 4000 logic series. To validate the PAElib, two use cases are presented. In the first use case, a 5-stage ring oscillator is described using PAElib and implemented with inverters from the 4000 series. This circuit was chosen, because it comprises only combinational logic and it can be tested without pattern generators or logic analyzers, as these tools can distort the power measurements. In the second use case a designer should choose between two implementations of a finite-state-machine (FSM): one implementation uses a binary counter with 4:1 multiplexers, the other one uses D type flip-flops and logic gates. The choice is not an obvious one, because consumption depends on (i) switching activity, (ii) input capacitance and (iii) power dissipation capacitance of the gates and (iv) parasitic capacitance of the connecting wires. This use case also is an example of using the PAELib to describe a circuit that contains both combinational and sequential logic. The less area demanding implementation was assembled on a prototyping board enabling us to further evaluate the PAELlib, in term of power estimation accuracy.

This paper is organized as follows: in Section II the main sources of power dissipation in CMOS digital circuits are briefly presented. The Section III describes the VHDL implementation of PAELib: components that monitors switching activity, static power and occupied area; creation of power&area aware gate models; creation of higher function circuits (counter, shift registes, etc.) with power and area estimation. Two use cases of the PAElib are considered in Section IV. Section V is dealing with future directions to make the VHDL library good for VLSI chip area and power estimation, increase its estimation accuracy. Finally, conclusions of the present work are drawn.


The total power dissipation of CMOS circuits has several components, resulting from different effects in the circuit [15]. A first, static component is due to subthreshold leakage currents of CMOS transistors when they are open, in saturation operating region. This component is present even in a quiescent state of the circuit. A second, dynamic component is caused by switching activity, logic level commutations in the circuit. This component is due to a few effects: capacitive switching; short circuit power (for a short time each transistor may conduct, thus a short circuit takes place between the supply and ground rails); glitch power (due to delays on the input ports of a gate). Traditionally, static power dissipation was neglected (less than 1% of the total power use for the logic families fabricated in CMOS technology) and dynamic power dissipation was considered the upholder for power dissipation. Nowadays, static power dissipation is getting more important in the power budget with the reduction of CMOS transistor feature size, thus not only dynamic power dissipation estimation, but also static power dissipation estimation is required.

A. Static power consumption

The static power computation [P.sub.static] is usually computed as the product of the subthreshold leakage current ICC (listed as quiescent current in the datasheets) of the CMOS device and the supply voltage VCC.:

[mathematical expression not reproducible] (1)

B. Dynamic power consumption

The significant part of dynamic power consumption is due to the energy required to charge and discharge the parasitic capacitances in the CMOS devices. The energy accumulated in a capacitance C is:

[mathematical expression not reproducible] (2)

where C is the capacity and V is the charging voltage.

For power modeling of CMOS devices, three parasitic capacitances are considered: the input capacitance of a pin []; the power dissipation capacity [C.sub.pd]; the parasitic capacity of the connecting wires [C.sub.load]. Note that, [C.sub.pd] is listed in CMOS device data sheet and its power dissipation is due to parasitic MOS transistor capacitances [16], short-circuit current and glitching. The measurement process of [C.sub.pd] for an arbitrary logic device can be found in [17]. The parasitic capacities [], [C.sub.pd] and [C.sub.load] of the CMOS inverter are illustrated in Fig. 1. When a commutation on the input signal occurs, these capacities are charged/discharged. Thus, the energy Etransition consumed for the transition is:

[mathematical expression not reproducible] (3)

It is customary to express the consumption in power, rather than energy. If an inverter is used in a circuit clocked at a given frequency, its power dissipation can be expressed as follows:

[mathematical expression not reproducible] (4)

where f is the frequency of the input signal.


PAELib is an extension of an earlier developed library PELib [14] that was deployed for static and dynamic power estimation only. As the circuits described in PAELib are structural descriptions, often realized at the gate level, the area estimation is carried out by carefully accounting the leaf component areas in the structural description. In the followings, the library structure is presented.

A. Library structure

The proposed VHDL library is composed of three packages: PAECore, PAEGates and Nbits, as in PElib [14]. The PAECore package contains the data types and utility functions used for power and area estimation. PAEGates contains power&area aware logic gate models from several CMOS logic family (CD4000, 74HC, 74AC to name a few). These power&area aware gate models may be used in structural descriptions, thus complex circuits with power and area estimation can be created. Examples of such circuits are in Nbits package that contains configurable length components such as registers, counters, etc. that are built using gates from PAEGates package. Total power & area estimate of a component is obtained by summing all the power & area estimates of each subcomponent/gate.
Figure 2. New data type definition for power and area estimation

type estimation_type is record
      dynamic : real;--meant to represent dynamic consumption
      static : real;--meant to represent static consumption
      area : real; ;--meant to represent occupied area
end record estimation_type;

Note: Table made from bar graph.

Figure 3. Overloading of "+" operator

function "+" (a, b : estimation_type) return estimation_type is
      variable sum : estimation_type;


      sum.dynamic := a.dynamic + b.dynamic;
      sum.static := a.static + b.static;
      sum.area := a.area + b.area;
      return sum;
end function;

B. PAECore package

As the natures of the power dissipation and occupied area are different, a new record data type, called estimation_type was declared with fields for the static / dynamic power and for the area. In Fig. 2, the definition of this user defined data type is given. As area and power estimates of gates had to be incremented for each component, it was straightforward to overload the "+" operator (the corresponding VHDL sequence is depicted in Fig. 3), thus addition supports estimation_type variables/signals.

Area estimation is implemented with the use of lookup tables. Such a lookup table - created by the user based on the logic gate datasheets - is illustrated in Table I. The lookup table cells contain the area occupied by a component, the lines and the columns denoting the logic family, respectively the functionality of the component. As we desired to estimate the number of ICs used, we completed the lookup table with 1 over the number of gates in an IC package. For example, the integrated circuit 74HC00 contains 4 NAND gates with 2 inputs, so the value of 1/4 is written in the corresponding cell of the lookup table. Note that, the lookup table could be also filled to obtain the NAND2 gate count equivalent of the circuit. For this, one must fill the cells with the NAND2 equivalent area.

For the area look-up table, a new data type, Area_values, is created in the PAECore package. Area_values is a matrix of LXT, where L is the number of logic series supported by the library and T is the number of supported component types. If the user wants to expand the library with a new series, he only needs to add a new line to this array, with the area values occupied by the corresponding gates. PAEcore also contains constant definitions for the parameters such as input capacitance [], leakage current ICC, power dissipation capacitance [C.sub.pd] for logic gates from several CMOS logic families (4000 series, 74HC series, etc.). Data is extracted from the datasheets of the logic gates and is stored in loop-up tables similar to Table I.

Pin toggle activity is accounted with the use of a component named activity_monitor (its source code is depicted in Fig. 4). This component should be connected to input and output (I/O) pins, in some cases to internal signals. A transition on any input pin will charge/discharge [] and [C.sub.pd]. A commutation on the output pin will have the same effect on [C.sub.load]. Whenever an I/O signal in the circuit is changing its logic level, a process is triggered and a counter is incremented. Thus, the charge and discharge of each parasitic capacity can be accounted. The input of the module is a signal called node and an event on the signal will trigger the transition_counter process. When the process is executed, an internal signal nr_trans is incremented. The output of the module is activity and it holds the number of transitions that took place on the input signal node. Glitches are considered as full transitions, although they may not have a full swing (supply to ground, or vice-versa).

The PAEcore package contains the PAestimator component (see its VHDL implementation in Fig. 5), which is instantiated in components, which are designated to be leaf components in the structural description. This module is developed to be highly parametrisable, allowing the user the configure the number of nodes where it is connected, the logic family and the functionality of the monitored component. The PAestimator has two inputs: sin - used to monitor switching activity of the input pins of a component (tracing the charge/discharge the [] and [C.sub.pd]); sout - used to monitor switching activity of the output pins of a component (tracing the charge/discharge of the load capacitance [C.sub.load]). PAestimator makes use of the activity_monitor to count the transitions on the input/output pins. As the number of transitions on a pin and the parasitic capacities connected to a pin are known, the total dynamic energy Edynamic due to the charge/discharge of the capacities can be computed as:

[mathematical expression not reproducible] (5)

where N and M are the number of input, respectively output ports; [I.sub.N] and [O.sub.M] are the number of logic level transitions (equivalent to the number of capacitor charge/discharge operations) on the Nth input, respectively on the Mth output Note that, the numbers [I.sub.N] and [O.sub.M] are obtained from activity_monitor components.
Figure 4. Signals activity monitoring (counting the number of

library IEEE;
use IEEE.std_logic_1164.all;

entity activitymonitor is
   port (node : in stdlogic;
       activity : out natural := 0);
end activity_monitor;

architecture behavioral of activitymonitor is
   signal nr_trans: natural := 0;
   transition_counter : process(node)
          nr_trans <= nr_trans + 1;
       end process;
   activity <= nr_trans;
end behavioral;

Static and dynamic powers are estimated as indicated by eq. (1), respectively eq. (5). Also occupied area lookup tables are carried out in PAestimator. PAEcore includes a component named power_estimator. In this module dynamic energy (Joule) is converted into power (Watt). The total power dissipation estimate Pestimate is the sum of static and dynamic power estimates Pstatc, respectively Pdynamic: [AE.sub.d]

[mathematical expression not reproducible] (6)

where [AE.sub.dynamic] is the dynamic energy consumed in AT time interval. The VHDL implementation of this module is given in Fig. 6. The sole input of the module is an estimation_type valued signal, which aggregates both static power and dynamic energy consumption. To obtain the total power consumption, the energy must undergo a conversion into power, thus a time window that corresponds to AT is required for the computation. The AT is passed as a parameter to the module and it is called time window. The output called power (with real type) gives the total power consumption.

C. PEGates package

This package contains primitives (logic gates, multiplexers, etc.) with the PAestimator component instantiated. Let us present the modeling of an AND gate to illustrate the use of the package. The model in Fig. 7 contains an AND gate with two inputs and one output (AND2). Beside the gate a PAestimator component is instantiated. This is configured to have inside 3 activity_monitor components, which are connected to each node of the circuit, in this case the I/O ports of the AND gate. Every logic level transition in the nodes is accounted in these components. The outputs of activity_monitor components are integer numbers, reflecting the pin toggle. This pin toggle information is used to compute the dynamic energy consumed to charge/discharge capacities in each node and their sum is also computed. The leakage current and the occupied area are looked upon from tables in the PAestimator component, thus enabling static power and area estimation. The estimates (area and static/dynamic power) are returned on a port named estimation with the data type estimation_type.

In Fig. 8 the VHDL description of the AND gate with area and power estimation from 0 is given. The entity of the AND gate is parametrized, to pass the logic family and the gate functionality. The architecture contains two parts: the first describes the functionality of the circuit, the second gets area and power estimates. The estimation is carried out in the PAestimator component. This is instantiated with the next parameters: the logic family and the gate values are passed further to the PAestimator component; as the AND gate has two inputs and one output signal, parameters N and M (which are the number of input, respectively output signals) are tied to 2, respectively 1.

D. Nbits package

Register transfer level (RTL) alike descriptions are enabled with the use of modules collected in the Nbits package. This package contains size parametrizable modules--N bit adder, N bit register, N bit ripple counter, etc.--built upon gates from the PAEGates package. The power and area estimate of a module are obtained by summing up all the estimations of internal gates. In Fig. 9 the model of an N bit register with power and area estimation is pictured. The register is built up using D type flip flops (DFF), which were implemented using gates from the PAEGates package. The power and area estimate of the DFF is the sum of the contained logic gate estimates. The DFF is instantiated N times in the register. The power and area estimate of the register is obtained by adding up all the DFF estimates.

In Fig. 10, the VHDL description of an N bit register is given. In the architecture a generate statement is used for repeated instantiations of DFFs, which are connected in a cascade. Each DFF has an estimation output. These outputs are summed up, thus resulting in the total consumption of the circuit. If only the N bit register power dissipation was to be measured, then the power_estimation component could be instantiated in the module, to obtain the total power dissipation, by adding the static and dynamic consumptions.


In this section two use cases of the PAElib are presented, to illustrate the potential applications of the library. In the first use case, the power and area estimate of a 5-stage ring oscillator is required. In the second use case, a designer should choose the less area demanding implementation of a finite-state-machine (FSM): one implementation uses a binary counter with 4:1 multiplexers, the other one built from DFFs and logic gates. The designer should also provide information about the power saving potential vs area overhead for each of the two implementations. This task is accomplished by the PAElib, allowing the designer to take informed design decisions in early design stages. The second use case is also an example of using the PAELib to describe the logic circuit that contains both combinational and sequential components. The less area demanding FSM implementation was assembled on a prototyping board.

A. 5-stage ring oscillator

In this use case, a 5-stage ring oscillator was modeled using the PAELib. The oscillator was also assembled on a prototyping board and power measurements were carried out. The measurement setup presented in Fig. 11 consists of the following components: an Analog Discovery DAQ [18] to supply the 5 V voltage for the circuit and measure the oscillation frequency with its oscilloscope channel, a 10 Ohm resistor as a high side shunt for current sensing, a CD4069UBE component for the inverter gates and a simple prototyping board. As the connecting wires have the capacitance around pF, a 47 pF load capacitance is placed after each inverter. In this way, the propagation delay of the inverters is predictable (can be found in the datasheet). The probe of the oscilloscope is connected to the last stage of the oscillator. The DAQ datasheet lists a 24 pF parasitic capacity for the probe. A 27 pF capacity is placed in parallel with the oscilloscope probe for frequency measuring, thus the total capacity in the node is 51 pF, approximately equal with the capacities in the other nodes. The voltage measured on the shunt resistance is 21.2 mV, so the total power consumption is 10.6 mW. The measured frequency was 1.06 MHz, the input capacitance [] = 6 pF, the power dissipation capacitance [C.sub.pd] = 12 pF and the load capacitance was 47 pF, except the equivalent capacitance of the frequency measurement node, which has approximately 51 pF. If one computes the dynamic power consumption using eq. (4) the result is 9.01 mW. The static power consumption in the case of the CD4000 series components is negligible. The estimated power using the VHDL library is 8.83 mW. The relative error between the measured and the estimated power is about 16%. Because the power estimation neglects the short circuit current (only the capacitor charge/discharge is accounted for) and no information about the wiring is available, the 16% relative error is an acceptable result. The PAElib dynamic power estimation accounts glitches as full swing transitions, thus overestimating the consumption.

The area estimate of the ring oscillator is 5/6, meaning that 1 IC chip should be enough for implementing the oscillator; actually this oscillator was implemented with a single CD4069 hex inverter.

B. Finite-state-machine

In the second use case, a FSM with the state diagram in Fig. 12 is given. Opposite to the ring oscillator, this circuit contains both combinational and sequential components. The designer has two options to implement the FSM: (i) with the use of a binary counter and 4:1 multiplexers; (ii) with DFF and logic gates. The task of the designer is to choose an implementation with the best area vs. power ratio. The consumption of the FSM depends on the switching activity, the input signals and the actual loads connected to the FSM, thus the choice is not an obvious one. One solution is to pass the FSM description to a power simulator, get power estimates and assess the area by hand. As an alternative, structural description using the components from PAElib will provide area and power estimates.

In Appendix A and B the schematics of the FSM based on a 74HC163 binary counter, respectively on a 74HC74 DFF are presented. Both schematics were described using the PAElib library. Simulation results (summarized in Table II) show that the DFF based FSM implementation is more power efficient. The static power with respect to the dynamic power is neglegible in both cases. The dynamic power was estimated for the 3 and 10 MHz operating frequencies. In both cases, the DFF-based implementation consumes less, approximately 10% percent power saving is possible. The estimated area for the counter-based FSM is 3.25, indeed the circuit takes 4 ICs to be implemented (see Appendix A.). The area estimate of the DFF based implementation is 4.66, indicating that at least 5 ICs should be used. The actual implementation would take up 7 ICs (see Appendix B). For this particular example the area estimate is too optimistic, because in one of the 74HC74 ICs only 1 DFF is used out of 2 and in the 74HC04 IC only 2 inverters are used out of 6.

To evaluate the power estimate of the PAElib, the counter based implementation was assembled on a prototyping board. The power measurement was carried out using a function generator (to generate the clock signal) and a voltage supply displaying the current drawn from the source, thus power consumption can be measured. In Fig. 13 the measured power versus frequency is plotted with a continuous line (the measured points with diamond). Note that the current display of the supply was a 4 digit one, thus the best resolution that can be measured is 1 mA [19]. The estimated power computed with VHDL power estimation is plotted with a square and the corresponding trendline with continuous line. The relative error between the estimated and measured power is approximately 20%. Considering that no information about the wiring and no short circuit power estimation is done, the above errors are acceptable.


A. Extending to VLSI chip power estimation

The utmost important development direction would be the extension to estimate the area and power of VLSI chips. The power estimation of logic gates from a standard CMOS library could be easily done: a SPICE test bench for each logic gate should be created and its input capacitance, power dissipation capacitance and leakage current should be obtained. unfortunately, the consumption of logic gates is not enough, also power due to clock distribution, memory and off chip loads should be estimated [20].

B. Power supply scaling

Due to transistor size reduction, static power dissipation is getting larger in CMOS circuits. One way to tackle the static power dissipation is the reduction of the supply voltage. Lately, power supply scaling [21] or partial shutdown is applied as a power saving approach. The proposed VHDL library could be easily modified to support static power estimation when the supply voltage is varying.

C. Increase CMOS dynamic power estimation accuracy

A possible way to increase the dynamic power estimation accuracy is by better modeling short circuit currents and glitches [22]. A recent solution to achieve glitch power modeling is by using waveform lookup [1]. The method could be implemented in VHDL.

D. Verification of the VHDL library against benchmarks

In this paper, the VHDL library is validated by comparing the estimated and measured powers of two test circuits, yielding acceptable results. But it is customary to compare the results for benchmark circuits such as ISCAS85 [23], largely recognized by the digital design industry.

E. Support for bipolar technologies

Another way of extending the VHDL library is the power estimation of logic gates built in bipolar technologies. Currently, TTL gates are less desirable as CMOS technologies are dominating the VLSI industry.


In this paper, a VHDL area and power estimation library is presented. The library is composed of 3 packages: PAECore package contains the necessary "infrastructure" for area and power estimation: user defined data types and operations, area look-up tables, modules for switching activity monitoring of nodes where parasitic capacities are charged/discharged and other utility functions; the PAEGates package contains modules that provide area and power estimated for several components for a few logic families; the Nbits package configurable size/width circuits (adders, counter, registers) implemented with gates from PAEGates package.

To illustrate the benefits of the library, two use cases were presented. In the first case a 5-stage ring oscillator was modeled with the help of the library and assembled on a prototyping board, yielding 16% power estimation error. In the second use case, a designer must choose between two implementations of a finite state machine. Area and power estimates were obtained using PAElib for the two implementations. Based on an informed design decision, the FSM was assembled using a binary counter and a few gates on a prototyping board, because it uses less area. The power consumption of the assembly was measured yielding 20% percent error. Considering that no information about the wiring, short circuit and glitching is available, power estimation accuracy is acceptable.


The counter-based implementation of the FSM in 0, is presented here. The counter control signals, the FSM states are listed in a table and the fields are filled considering the desired state transitions. The control logic is implemented with 4 to 1 MUX and OR logic gates. The obtained schematic was assembled on a prototyping board with off-the-shelf components, it was functionally verified and power measurements were carried out.

The 74HC163 counter is used to hold the current state coded on 3 bits. These 3 bits are taken from the [Q.sub.C][Q.sub.B][Q.sub.A] outputs of the counter. The counter can perform count, load, hold and combined operations (ie. count/load, count/hold, etc.). The operations for state transitions are noted beside the state in 0. Counter control signals (load - LD and hold - P&T) are filled for each state. In Table III, the truth table of the FSM is listed. The control signals are parameterized by a and b control signals. Based on this table the logic functions for control signals LD, P&T, A, B, C are derived, ultimately the logic functions are implemented using 4:1 multiplexers, OR gates and inverters (see 0). The functional verification of the FSM was carried out manually by inspecting the waveforms obtained with the Analog Discovery's logic analyser [18]. In the setup a and b had constant logic levels of 1, respectively 0. A screenshot of the logic analyser is depicted in Fig. 14. One can follow the state transitions and compare it against the specifications in the FSM diagram, thus the implementation correctness is examined.


The DFF-based implementation of the FSM from 0 is derived. After completing the state transition table, the combinational circuits for each DFF data input is derived and an implementation with off-the-shelf components is obtained (0).

In Table IV, the state transition table, parametrized by two input signals a and b of the FSM is listed. Three 74HC74 DFFs are used to hold the current state, connected to the non-inverting outputs of the flip-flops: Q2, Q1 and Q0. The next state, represented on D2, D1 and DO signals are parametrized by two input signals a and b. Based on this table the logic functions D2, D1 and D0 are minimized using two level heuristic logic minimization [24], ultimately the logic functions are implemented using AND and OR gates (see 0).


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Botond Sandor KIREI, Verginia-Iulia-Maria CHEREJA, Sorin HINTEA, Marina Dana TOPA

Technical University of Cluj Napoca, 410011, Romania

This work was supported by a grant of the Romanian National Authority for Scientific Research and Innovation, CNCS/CCCDI--UEFISCDI, project number PN-III-P2-2.1-BG-2016-0268, within PNCDI III.

        AND2   AND3   OR2    OR3    NAND2  DFF    ...

74HC    1/4    1/3    1/4    1/3    1/4    1/2
74HCT   1/4    1/3    1/4    1/3    1/4    1/2
74AC    1/4    1/3    1/4    1/3    1/4    1/2
74ACT   1/4    1/3    1/4    1/3    1/4    1/2
CD4000  1/4    1/3    1/4    1/3    1/4    1/2


FSM implementation  Power                            Area
                    static        dynamic
                                  @3 Mhz    @10 Mhz

74HC163 + 4:1 mux   220 [micro]W  20.2 mW   66 mW    3.25
74HC74 + gates      40 [micro]W   18.2 mW   60.3 mW  4.66


Current state  Operation    Control signals
QCQBQA                      Cl   Ld   P,T  C    B    A

000            Count/Hold   1    1    a    x    x    x
001            Count        1    1    1    x    x    x
010            Load         1    0    x    1    0    1
011            x            x    x    x    x    x    x
100            Count/Load   1    b    1    0    0    1
101            Count/Hold   1    1    a    x    x    x
110            Load         1    0    x    0    0    0
111            x            x    x    x    x    x    x


Current state  Next state
Q2   Q1   Q0   D2   D1   D0

0    0    0    0    0    a
0    0    1    0    1    0
0    1    0    1    0    0
0    1    1    x    x    x
1    0    0    !b   0    1
1    0    1    1    a    !a
1    1    0    0    0    0
1    1    1    x    x    x
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Article Details
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Author:Kirei, Botond Sandor; Chereja, Verginia-Iulia-Maria; Hintea, Sorin; Topa, Marina Dana
Publication:Advances in Electrical and Computer Engineering
Article Type:Case study
Date:Feb 1, 2019
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