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Optimization of CNFET parameters for high performance digital circuits.

1. Introduction

CMOS technology faces significant challenges at the nanoscale due to several factors like short-channel effects, a lack of control over static leakage current and source-to-drain tunneling [1,2]. Now in order to sustain Moore's Law, it is necessary to look for alternatives like Carbon Nanotube Field Effect Transistors (CNFETs) that have received a lot of attention in the past few years as a promising extension to silicon CMOS for future digital logic integrated circuits. CNFETs show desirable characteristics such as high mobility of electrons movement near ballistic transport and the ability to carry large current and smaller device footprint as compared to conventional Si-MOSFETs [3]. Carbon nanotubes (CNTs) are a promising material for flexible electronics which offer a wide variety of applications such as flexible solar cells, skin-like pressure sensors, and conformable RFID tags [4].

CNFET has many applications in digital circuits such as arithmetic circuits, Full Adder-Subtractor [5-7], and 6T SRAM [8] and there is hybridization between MOS and CNFET to improve performance for digital [9] or analog design [10]. Efforts have been made in recent years on modeling and simulating CNT related devices such as CNFET [11, 12] to evaluate the potential performance at the device level. Various optimized schemes are suggested and demonstrated to minimize the effect of parasitic capacitances and thus improve the speed of CNT ICs [13].

There has been a previous work which investigates optimum design parameters to propose the suitability of pure and hybrid CMOS-CNFET in a wide range of high performance analog circuits [14]. In this paper, we discuss the design parameters of the CNFETs and show how to optimize these parameters for obtaining high performance CNFET for digital circuit implementation. The optimization is performed using HSPICE for extensive simulations. The results obtained are useful for understanding the design parameters of near ballistic CNFETs and for identifying important issues to further improve CNFET performance.

This paper is organized as follows: the structure and basic characteristics for CNFETs are discussed in Section 2. Section 3 describes the effect of all design parameters on the performance of CNFETs. Section 4 gives the results and discussion. Finally, a concluding remark is given.

2. Carbon Nanotube Field Effect Transistors (CNFETs)

Both theory and experiments have demonstrated that a single walled carbon nanotube (SWCNT) can be either metallic or semiconducting, depending upon the arrangement of carbon atoms. This is decided by its chirality (Ch) whose magnitude is given by (1) and its relationship with CNT diameter ([D.sub.CNT]) is given by (2), where "a" is the graphene lattice constant (0.249 nm) and [n.sub.1], [n.sub.2] are positive integers that specify the chirality of the tube

Ch = a[square root of [n.sup.2.sub.1] + [n.sup.2.sub.2] + [n.sub.1] + [n.sub.2]], (1)

[D.sub.CNT] = Ch/[pi]. (2)

CNFETs use a number of semiconducting SWCNTs as a transistor channel, as shown in Figure 1. The two ungated portions source and drain are heavily doped semiconducting CNTs with Palladium (Pd) as metal contacts while the CNT channel is undoped. The CNFET operates similar to that of a traditional MOSFET. The CNFET exhibits unipolar behavior and operates on the principle of barrier height modulation when applying a gate potential [14]. The CNFET offers many potential advantages with respect to silicon-based technology. This is due to its excellent electrical and structural characteristics such as quasi-1D ballistic transport of electrons, higher drive current, large transconductance, near ideal subthreshold slope, low intrinsic capacitance, and strong covalent bonding [15].

The CNT diameters, the channel width (W) of the CNFET transistor, the number of CNTs (N) in the channel of a CNFET, and internanotube spacing (S) are related by (3). The band gap energy ([E.sub.g]) and the threshold voltage ([]) of the intrinsic CNT channel are related by (4):

W = (N-1) S + [D.sub.CNT], (3)

[][approximately equal to][E.sub.g]/2 x e. (4)

The high performance HSPICE model has been used for analyzing the performance of CNFET transistor and 32 nm Si-MOSFET. The CNFET model successfully accounts for its device parasitic and practical nonidealities. Apart from accurate predictions of dynamic and transient performances, the model gives more than 90% accuracy [11].

3. Optimization of Pure-CNFET Parameters

This section presents our simulation experiments to optimize the design parameters of the pure-CNFET. The pure-CNFET is designed in terms of optimum structural device parameters such as CNT diameter ([D.sub.CNT]), number of perfectly aligned nanotubes (N) with uniform internanotube spacing (S), and oxide thickness ([T.sub.ox]) in addition to the selection of operating supply voltage. In these simulation experiments, the channel length of the CNFET is adjusted at 32 nm to be identical with that of Si-MOSFET for a fair comparison.

The optimization results presented in this section are obtained from several runs with different setups, where the original parameter values are listed in Table 3.

3.1. Optimum Supply Voltage. Both the static and dynamic powers will decrease with decreasing the supply voltage ([V.sub.dd]); that is, an effective way to reduce the power dissipation is to scale down the supply voltage of the circuit [15]. Extensive simulation experiments using HSPICE are carried out to study the effect of [V.sub.dd] on the delay and power consumption of CNFET, hybrid (NMOS-PCNFET), and CMOS inverters at 32 nm technology node. Figure 2 gives the simulation results of the average delay at different values for the supply voltage. It is observed from Figure 2 that hybrid inverter has shorter delay than the conventional MOS at all values of the supply voltage. But CNFET inverter has the shortest delay due to its higher current driving capability. The CNFET-based inverter does not offer minimum power consumption as shown in Figure 3. To obtain low PDP with acceptable supply voltage, the 0.6 V is chosen as a supply voltage.

3.2. Optimum CNT Diameter. Diameter is the main parameter that affects the on-current proportionally in a CNFET. Using a larger diameter reduces the band gap; therefore the on-current increases as shown in Figure 4. This is because the transconductance goes up with the increase in diameter of the nanotubes.

But at the same time, the leakage current is increased as well. The simulation results are illustrated in Table 1 showing degradation in [I.sub.on] to [] current ratio. This problem should be handled with care, because digital circuits require high on-currents, but also very low off-currents.

As shown in Figure 5 large diameter deteriorates the power handling capability as CNTs become more conducting. This is due to the inversely relation between the diameter and []. When [] decreases for large diameter, the power consumption will increase. However, the switching speed increases and the device approach saturation faster. This is also observed in Figures 6 and 7 showing the large effect of diameter variations on delay and PDP for pure technology design.

Furthermore, the selection of the suitable diameter will depend on the value of PDP. The optimum diameter is 1.49 nm which is determined according to chiral vector (19,0) of the nanotubes.

3.3. Optimum Number of CNTs. Single nanotube based transistor is not suitable to provide competitive performance over a traditional MOSFET. It is necessary to determine the number of CNTs to be used in an array in order to guarantee sufficient current supply.

In this section the problem associated with large number of tubes is investigated in addition to geometrical constraints. The on-current approximately is given by (5), where [g.sub.CNT] is the transconductance per CNT, [L.sub.s] is the source length (doped CNT region), and [[rho].sub.s] is the source resistance per unit length of doped CNT [11]:

[I.sub.CNFET][approximately equal to][Ng.sub.CNT]([V.sub.dd] - [])/1 + [g.sub.CNT][L.sub.s][[rho].sub.s]. (5)

It is worth noting that the total current drive in a CNFET depends on the number of CNTs per device ("W"). This explains the increase in current driving capability of the device with increasing the number of CNTs.

However, increase in number of CNT also incurs penalty in power dissipation which is clear in Figure 8.

The percentage of decreasing delay with N is larger than the increasing of average power consumption as shown in Figure 9. Thus, keeping all the design metrics such as power, delay, and PDP in mind, it is observed from Figure 10 that the PDP decreases with increase in number of CNT. This is due to the increase in the driving current and hence reduction in delay, which outweighs the increase in power dissipation.

We conclude that the upper limit on the number of CNTs used is determined by the power-performance trade-off but still looking at the overall performance merits. To maximize circuit performance at the 32 nm node, a minimum CNT density of 200 CNTs per [micro]m gate width is desired [16]. Also in another research the optimum value of "N" comes out to be 250/[micro]m with equal spacing [10] which is nearly matched with our optimization. From previous results, the optimum number of CNT is 8.

3.4. Optimum Internanotube Spacing. The drain current of the CNFET is dependent on pitch value (internanotube spacing), which determines the amount of screening effect. Figure 11 shows the drain current with different values of pitch and number of tubes.

[I.sub.on]/[] can be enhanced by increasing the pitch due to weakening the charge screening effect. However a larger pitch degrades the integration density. So, the trade-off between [I.sub.on]/[] and area efficiency must be considered.

With decreased intertube spacing (pitch), the gate-to-channel capacitance and the resulting current produced by a nanotube are reduced due to increasing screening effect which is shown in Figure 12. Charge screening reduces the effective width of the channel, thereby degrading the device current [11,17]. But shorter pitches are desirable to enhance the integration density of a chip with CNFET technology.

It can be noted from Figure 13 that the minimum delay is achieved by placing the nanotubes far apart (to increase [I.sub.PER TUBE]). Note that, for 1 nm of CNT diameter with 2 nm of Hf[O.sub.2] dielectric thickness, the optimal spacing for high parasitic load is 1.6x the diameter. It is worthwhile to mention that the optimal S depends on the choice of diameter and the dielectric thickness [18]. After seeing results plotted in Figure 14, it can be noted that the PDP decreased slowly after pitch = 6 nm. So, we take the area trade-off into account. Thus we can say the best pitch value is 6 nm.

3.5. Selection of Dielectric Material. The top-gated CNFETs have been fabricated using 15-20 nm thick Si[O.sub.2] as a gate insulator. To improve the device performance further, a thinner gate insulator with a higher dielectric constant can be used. Recently, high dielectric materials such as Zr[O.sub.2] and Hf[O.sub.2] thin films have also been employed as the insulator in top-gated CNFETs [19]. The dielectric materials that are generally considered are listed in Table 2 along with their dielectric constants ([K.sub.ox]).

The saturation current of CNFETs increases with increasing dielectric constant as shown in Figure 15 but the degree of this positive effect decreases as we go for higher dielectric material. This means that as we are going for higher and higher dielectric constant materials the increment in drain current with respect to [K.sub.ox] reduces [20].

Zirconium oxide (Zr[O.sub.2]) and hafnium oxide (Hf[O.sub.2]) are the forefront of materials science semiconductor electronics [19]. In our optimization, [Zro.sub.2] is used as a gate insulator with high K dielectric constant.

The speed advantage of CNFET over MOSFET technology is sensitive to the gate parasitic capacitance [16]. As the oxide thickness increases, the gate-to-channel capacitance deceases as shown in Figure 16 and therefore the device delay reduces. But by increasing the oxide thickness, the driving current decreases; therefore [I.sub.on]/[] ratio is decreased as shown in Figure 17. Thus, there is a trade-off between the current drive per device and speed. To improve the performance of the device, the oxide thickness of high K dielectric material must be chosen with care.

For inverters designed based on pure-CNFET, the dynamic power consumption and delay are plotted in Figures 18 and 19 for certain range of oxide thickness of Zr[O.sub.2]. The power delay product is also computed to choose optimum oxide thickness. The less value of PDP is at [T.sub.ox] = 2.5 nm. But there is no great difference between [T.sub.ox] = 2.5 nm and 1.5 nm. So, we can say the optimum oxide thickness is 1.5 nm at [K.sub.ox] = 25.

3.6. Selection of Contact Material. The contact between semiconducting CNT and metal is generally modeled as a Schottky barrier (SB), resulting from the Fermi level mismatch between semiconducting CNT and metal electrode [21,22]. For a typical p-type CNT transistor, the metal with high work function forms small SB height contact, schematically, where the Fermi level of the metal aligns well with the valence band of the CNT. By eliminating the Schottky barrier between the source contact and source material, the transistor will be capable of delivering more on-current.

Palladium (Pd), which is a noble metal with high work function and good wetting interactions with CNT, has been found with good electrical contact to both semiconducting and metallic CNTs [23].

4. Results and Discussion

After selecting the best design parameters and ensuring by the simulation results that high performance is obtained for the CNFET device, we applied these parameters in basic logic gates (Inverter, NAND, and NOR) for optimized CNFET and compared them with nonoptimized CNFET, Si-MOSFET, and hybrid configuration. We summarize the nonoptimized and proposed optimized parameters of CNFET in Table 3.

From the results shown in Table 4, nonoptimized CNFET has the smallest delay for the inverter and NOR design compared to optimized CNFET, hybrid (NMOS-PCNFET), and Si-MOSFET. But the optimized CNFET saves area by 75% rather than the nonoptimized CNFET.

For the average power consumed, the hybrid configuration is better than nonoptimized CNFET but optimized CNFET shows the best design for all logic gates compared to nonoptimized CNFET, hybrid, and Si-MOSFET according to the results listed in Table 5.

The percentage improvement in power consumption is greater than the percentage improvement in propagation delay. So, this good result reflects the PDP term.

From PDP results as listed in Table 6, hybrid configuration is better than nonoptimized CNFET for PDP term for NAND logic gate. But optimized CNFET is better than the hybrid configuration for all basic logic gates. The power delay product of the optimized CNFET is about 68%, 63%, and 79% times less than that of the nonoptimized CNFET circuits, hybrid configuration, and Si-MOSFET, respectively. It can be summarized that optimized CNFET has the smallest PDP for all basic logic gates.

5. Conclusion

The influence of device design parameters of 32 nm pure-CNFET on the delay-power product and overall performance has been explored in this paper. First, we investigated the influence of supply voltage on device performance and chose the optimum supply voltage. Then, we studied the effect of design parameters on speed, power, and area saving. The nanotube diameter, the number of nanotubes per device, and intertube pitch play the most important roles in determining both the area (physical gate width) and performance ([I.sub.on]/[]) of carbon nanotube transistors. Trade-off among area efficiency, Ion, and [I.sub.on]/[] of CNFETs are explored in this paper. Further performance improvement can be achieved by using a smaller diameter with upper range of number of CNTs with smaller pitch. We also reduced the thickness of dielectric with high-K material. Choosing Pd as a contact material is another factor to enhance the overall device performance. Finally, the results show that the design based optimal design parameters of CNFET have the smallest value of PDP compared to nonoptimized, hybrid, and Si-MOSFET designs for all basic logic gates.

Competing Interests

The authors declare that they have no competing interests.


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Shimaa Ibrahim Sayed, Mostafa Mamdouh Abutaleb, and Zaki Bassuoni Nossair

Electronics, Communication, and Computer Engineering, Helwan University, Helwan, Egypt

Correspondence should be addressed to Shimaa Ibrahim Sayed;

Received 11 March 2016; Accepted 14 July 2016

Academic Editor: Anna Richelli

Caption: Figure 1: CNFET structure.

Caption: Figure 2: The propagation delay of pure-CNFET, hybrid and CMOS inverters for different supply voltages.

Caption: Figure 3: The average power consumption of pure-CNFET, hybrid, and CMOS inverter for different supply voltages.

Caption: Figure 4: The current with variations of diameter of CNT for pure- CNFET.

Caption: Figure 5: Effect of diameter variations on average power consumption for pure technology design.

Caption: Figure 6: Effect of diameter variations on average delay for pure technology design.

Caption: Figure 7: Effect of diameter variations on PDP for pure technology design.

Caption: Figure 8: Average power versus number of carbon nanotubes for pure-CNFET inverter.

Caption: Figure 9: Delay versus number of carbon nanotubes for pure-CNFET inverter.

Caption: Figure 10: PDP versus number of carbon nanotubes for pure-CNFET inverter.

Caption: Figure 11: On-current versus pitch for different number of carbon nanotubes.

Caption: Figure 12: Cross-sectional view of a multitube CNFET.

Caption: Figure 13: The effect of pitch on delay for pure-CNFET inverter.

Caption: Figure 14: The effect of pitch on PDP for pure-CNFET inverter.

Caption: Figure 15: The on-current versus number of carbon nanotubes for different dielectric constants.

Caption: Figure 16: The gate parasitic capacitance with oxide thickness.

Caption: Figure 17: The on-current with different oxide thickness.

Caption: Figure 18: The average power for oxide thickness at [K.sub.ox] = 25.

Caption: Figure 19: The delay for oxide thickness at [K.sub.ox] = 25.
Table 1: Showing different diameter values with [] and
[I.sub.on]/[] ratio.

Chirality                (13,0)   (17,0)   (19,0)   (22,0)   (26,0)

Diameter (nm)              1       1.33     1.49     1.72      2
[] (V)           0.422     0.32     0.3      0.24     0.2
[I.sub.on]/[]    1192     55.5     22.8     6.95    2.016

Table 2: List of oxides considered for gate insulation with their
dielectric constants.

Name of the oxide   Chemical formula   Dielectric constant ([K.sub.ox])

Silicon dioxide       Si[O.sub.2]                      4
Hafnium dioxide       Hf[O.sub.2]                     16
Zirconium dioxide     Zr[O.sub.2]                     25

Table 3: List of design parameters for nonoptimized and optimized

Design parameter               Nonoptimized        Optimized

Supply voltage (V)                 0.9                0.6
CNT diameter (nm)                  1.5                1.5
Gate dielectric constant:    Hf[O.sub.2] (16)   Zr[O.sub.2] (25)
Oxide thickness (nm)                4                 1.5
CNT pitch (nm)                      20                 6
Number of CNTs                      10                 8
Work function contact (eV)         4.5                5.1

Table 4: The propagation delay of inverter, 2-input NAND, 2-input NOR
gate for Si-MOS, pure-CNFET, and hybrid configuration.

                             Delay (xE-11S)

                Si-MOSFET                                 Hybrid
                32 nm CMOS   Nonoptimized   Optimized   NMOS-PCNFET

Inverter          14.6          3.80           9.51        5.94
2-input NAND      19.95        11.94          16.09        9.91
2-input NOR       20.50         7.54           9.95       10.17

Table 5: The power dissipation of inverter, 2-input NAND, and 2-input
NOR gates for Si-MOS, pure-CNFET, and hybrid configuration.

                                 Power (xE-07W)


               Si-MOSFET                                 Hybrid
               32 nm CMOS   Nonoptimized   Optimized   NMOS-PCNFET

Inverter          5.83         13.19         2.61          9.76
2-input NAND     13.98         17.26         3.53         12.35
2-input NOR      10.05         16.14         3.88         14.23

Table 6: The power delay product of inverter, 2-input NAND, and 2-input
NOR gate for Si-MOS, pure-CNFET, and hybrid configuration.

                                        PDP (xE-17J)

               Si-MOSFET                                   Hybrid
               32 nm CMOS   Nonoptimized   Optimized     NMOS-PCNFET

Inverter          8.51          5.01         2.48            5.79
2-input NAND     27.80         20.61         5.68           12.23
2-input NOR      20.60         12.16         3.86           14.47
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Title Annotation:Research Article
Author:Sayed, Shimaa Ibrahim; Abutaleb, Mostafa Mamdouh; Nossair, Zaki Bassuoni
Publication:Advances in Materials Science and Engineering
Article Type:Report
Date:Jan 1, 2016
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