Next-generation RF devices impact test.
The test requirements also are changing to include added modulation tests and DSP requirements, concurrent test capability, and more multisite testing. Both sets of trends impact costs.
New standards for wireless communications are expanding mobile handset capability at a seemingly relentless pace. Just as relentless is the pace of competitive cost pressure.
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The next generation of wireless semiconductors appears to threaten cost-reduction objectives. New RF standards tend to require either new transmission frequencies or new noninterference capabilities with respect to existing RF signals. But, new RF products maintain compatibility with previous standards: Backward compatibility with the installed network enhances the value of both the wireless network and the new devices.
As a result, chip hardware which otherwise might have been eliminated by a new standard still is required due to backward compatibility with existing infrastructure, be that base-station networks or existing WLAN access points.
Device vs. RF Pin-Count
Third-generation (3G) cellular RF transceivers include both existing quad-band GSM/EDGE standards and dual/triband WCDMA capability. Triband and quadband GSM/EDGE transceivers typically have five to seven RF connections. Adding WCDMA bands with diversity receive channels increases the total RF pin-count to the 14 to 20 range depending on implementation of the RF chip.
Pin-counts on WLAN devices also are increasing to accommodate multiple-input multiple-output (MIMO) capability. In addition to expanding spectral efficiency by near-integer multiples, the number of RF pins also expands by precisely integer multiples. A 4x4x MIMO WLAN access point has 16 RF pins, four transmit and four receive for each of two frequency bands, plus an additional connector for either a reference clock input or a local oscillator test input.
The installed base of RF ATE has either eight or 12 RF test interface ports, adequate for the dual/triband 2G transceivers for which they were purchased over the last six to eight years. In rare cases, 16 RF ports are available.
The new devices simply don't fit on existing 2G testers. Even using device interface board (DIB) circuits, the site capability of 2G testers will be reduced to single-site, rather than dual-site or quad-site testing. Plus, with each device's RF paths increasing by more than double, test time per site--assuming equivalent fault coverage test--also is likely to double.
As a result, the amount of time each transceiver is physically on the tester threatens to quadruple. If a fully depreciated 2G tester and handler resulted in an hourly rate reduction of 75%, then perhaps the per-site test time increase would be manageable. This is unlikely because the depreciation of the tester, handler interface kit, and handler components of volume work-cell rates is between one-third and one-half of typical hourly rates. At best, work-cell rates could be halved, resulting in a net doubling of test cost due to the increase in device complexity.
Impacts of SOC/SIP Integration
RFSOC devices are mainly digital and cache memory chips with less than half their physical area dedicated to RF, power management, converters, and analog circuits. The RF and mixed-signal circuits normally are not testable during the noise-inducing digital tests so digital scan and functional test time are added to the RF and analog test time. Since digital scan typically requires more time than the RF testing, once again the amount of time on a 2G tester will become unacceptably high.
Multisite test counters the cost impact of the RFSOC's longer test times. Boosting multisite for high pin-count RFSOCs forces the tester configuration to 60+ RF ports simultaneously with 1,000+ digital pins and 70+ DC pins, including four-quadrant VIs with current sink capability. 2G testers, which typically have 64 to 128 digital pins, were not built for this requirement. From both economical and functional perspectives, it would appear that 2G testers will not be useful for next-generation RFSOC test due to the inability to support multisite.
Compared to RFSOC, RFSIP is uniquely flexible. SIPs offer rapid time-to-market because of performance/cost optimized front-end fabrication processes. Further cost savings are possible by embedding passives within the SIP substrate, effectively removing a later pick-n-place step for the end-device assembly. However, SIPs add a cost layer through yield loss in the multiple known good die (KGD) attached to the SIP substrate.
Any of the multiple die in the RFSIP can induce a failure. Bare die are tested at the wafer level to assure KGD. RF presents challenges to test correlation between probe and SIP package test and, consequently, KGD assurance.
The placement of passives, which are necessary for RF die operation, is different between the probe card and the passives in the SIP package. The values of the passives also vary, which can cause correlation problems between the die-level and SIP-level measurements. The device sees two slightly different electrical environments and may behave differently. The behavior needs to be correlated over many devices and against variances in the passives to ensure against false failures or escapes into the SIP device.
In today's typical RF production processes, RF devices are DC-tested only. In the uncommon cases where RF tests are run, the specified worst-case accuracy for each usually is in the 0.6- to 1.0-dB range.
The desired end-device test accuracy is 0.2- to 0.3-dB maximum error. This is challenging for three reasons:
* Systems used for RF probe test tend to be older models than the package testers. The measurement uncertainties are different, and tester calibration has differing traceability paths to accepted standards.
* RF probe cards can be difficult to de-embed from the measurement data; that is, measurements included both characteristics of the probe card and the device rather than only the device.
* The position of passives can alter the parametric behavior of the die's RF circuits.
Maintaining a robust yield process to less than 0.3 dB without somehow improving the metrology and accuracy performance of the installed base of 2G testers is very difficult.
Test Control and DSP Architecture
3G standards are full duplex; simultaneous transmission and reception are used. Prior standards in use today are half duplex; the handset transceiver alternates between transmitting and receiving. Most 3G devices can at least partially be tested in full-duplex mode. This creates an opportunity to reduce test time through simultaneous transmitter and receiver testing.
2G testers, unfortunately, were designed for half duplex transceivers, devices that did not permit concurrent transmitter and receiver testing. While appropriate instrumentation may be present, the 2G testers lack the control architecture necessary to simultaneously adjust instrument settings and subsequently actuate simultaneous data acquisition of the device's RF signal and analog IQ signals.
Instead, 2G testers must sequentially command setup and level settling functions to the RF stimulus instruments and then to RF measuring instruments. Digitizers usually are shared in 2G testers; both the setup and the actuation of RF and analog IQ samples must be done sequentially. This architectural limitation of 2G testers would seem to prevent testing of 3G transceivers with the preferred full-duplex method.
The architectural limitations of 2G testers include four basic categories of common test functions:
* Concurrent setup of the various instruments used during a device test.
* Concurrent triggering of data acquisition on single or multiple sites, typically using pattern control.
* Movement of captured data from instrument memory to a memory location accessible by a DSP.
* Processing of the captured signal in the DSP without impeding continuation of the testing process.
Concurrent setup of individual instruments in 2G testers is not possible because the host computer is intensely involved with the process of recalling the instrument parameters, issuing driver commands to effect those settings, and then waiting for the instrument's signal characteristics to settle. For example, some 2G testers frequently share instruments such as voltmeters across multiple device pins. This was logical in a host control limited architecture because the host can control only one meter's setup and data acquisition process.
Adding multiple meters per device pin doesn't improve test time because the host-limited control process cannot command them simultaneously. Today, SOC testers use local instrument memory and microcode to simultaneously command setup processes with a single, pattern-driven, or command-line device statement.
Concurrent triggering of data acquisition similarly is difficult for 2G testers because the control of that process is intensively tied to the host controller rather than to local instrument-controlled processes.
Foreground movement of the capture data from the capture memory to the DSP uses test time on 2G testers. That is, the test device(s) physically sits on the DIB's test sockets while the host computer tells the instrument capture memory to send the acquisition data array over a data bus to the DSP's memory.
The data bus, if shared among multiple capture instruments, must be used sequentially for the data movement process. The total increase in test time depends on the number of tests, the number of capture instruments, the latency of the command process, the amount of data per capture, and the rate of data packet movement to DSP memory.
Today, SOC testers actuate data movement under instrument-resident microcode commands. Data is transferred from capture memory to the DSP without the involvement of the host computer. As a result, the host computer is free to proceed to subsequent tests. This capability is called background DSP.
A 2G tester's DSP usually is the host processor. While the host processes data, it is not available to conduct tests. As the complexity of wireless devices has grown, so have the DSP requirements for tests such as error vector magnitude (EVM), blocker tests, and bit error rate (BER).
As a result, test times would approximately double linearly with respect to site count assuming devices had the same number of RF paths or, generally, equal to the number of RF connections. However, since RF paths are more than doubling, the effect is potentially a 4x impact.
Today, SOC testers have multiple DSPs separate from the host controller. The separate DSPs allow background processing while the controller concurrently proceeds with other tests.
Since the mid-1990s, RF-focused testers have successfully served and been subsequently optimized for an array of 2G, Bluetooth, and WLAN devices. The next generation of these devices is different in multiple aspects including increased RF pins; added digital, memory, and power management circuits; simultaneous Tx/Rx operating modes, MIMO capability, and increased need for modulation and KGD testing. The potential cost impact is unacceptable to semiconductor manufacturers and handset manufacturers alike.
Upcoming in This Series
This is the first article in a three-part series discussing the likely test cost impacts of next generation consumer wireless semiconductors. The second article, which will appear in the November issue of EE, examines key performance aspects of upcoming and future device generations to assess where instrumentation improvements are most likely. In the December EE, the third article will synthesize the combined needs and propose a cost structure and system-level requirements based on established multisite economic principles.
About the Author
Ken Harvey is responsible for the RF product line architecture at Teradyne. The 20-year veteran of the ATE industry has a background in RF/microwave and graduated from the University of Akron with a B.S.E.E. and Santa Clara University with an M.B.A. Teradyne, MS 600-2, 600 Riverpark Dr., North Reading, MA 01864, 978-370-3670, e-mail: email@example.com
by Ken Harvey, Teradvne
RELATED ARTICLE: RF Built-In Self-Test
One approach to cost reduction of RFSOC tester configurations is eliminating the RF instrument, which ranges between one-fourth and one-fifth of the work-cell capital expense (CapEx). Since CapEx-related depreciation is between one-third and one-half of a typical hourly work-cell rate, RF BIST (built-in self-test) can cut costs by 8% to 12%. Assuming RF BIST could be implemented without increasing test time, costs could be reduced by an amount between one and two pennies for a high-volume, next-generation RFSOC device.
While there is the potential for RF BIST to be helpful, it also is elusive. RF devices are highly regulated for both output power level and frequency content. Radio standards also rely on minimal spectral regrowth and precise level controls to maximize base-station capacity. And, new performance requirements are being added to standards to maximize the efficiency of data transmissions, which in fourth-generation cellular proposals is expected to exceed 100 Mb/s.
More importantly, the rapid evolution of RF standards in a profit-challenged business environment means that many companies lack the extra design time and resources needed to make RF BIST routinely production-worthy. Except for extremely high-volume chip designs for older, better-known standards, RF BIST has not been feasible.
Constantly changing standards and design implementation for those standards create a moving target for generalized RF BIST techniques. There are many different approaches to RF BIST. So far, none appear to apply universally across the varying device fault coverage and RF standards requirements.
Approximate Device Change 2G Tester Limitation Test Cost Impact Cost Increase >2x Increase in 8 to 12 RF Pins Dual Site Reduced 2 to 3x RF Connections Total to Single Site >2x Increase in Data Moves and Each Path Tested 2x RF Connections Host-DSP Add Test Serially Plus Time Data and DSP Handling Digital Pin- 64 to 128 Digital Adds Scan Test 2 to 3x Count in Pins in Typical Time RFSOC/SIP Configurations RFSIP Need for RF Tester at Probe Yield Loss Process KGD and Package Need Dependent High Accuracy Modulation Test Data Moves and DSP Additional Test 2x Requirements Occur in Foreground, Time Add Test Time Concurrent Test Lack of Parallel Additional Test 2x Opportunity Control Architecture Time Impact of Next-Generation Consumer Devices on 2G Tester Costs
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|Title Annotation:||IC ATE|
|Date:||Oct 1, 2007|
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