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New Materials Prompt New Reliability Issues.

Novel semiconductor materials have numerous implications on process monitoring instrumentation and test techniques.

Semiconductor device reliability can be divided into two types: infant mortality failures and wearout mechanisms. Infant mortality failures occur because of manufacturing defects. The sources of these defects are usually the same as those that cause yield loss, so instrumentation requirements for detecting both are similar.

Wearout failure mechanisms are physical degradation mechanisms that eventually cause the device to fail. For the reliability assurance engineer, the challenge is to make the rate of degradation slow enough so only an insignificant percentage of the population will fail in the specified "useful lifetime" of the device.

As semiconductor devices trend toward smaller geometries, denser packing, faster speeds, and lower power consumption, the requirements for instrumentation to monitor reliability will become more severe. Technological advances will be continuations of existing trends, such as moving toward thinner gate oxides.

Semiconductor technology has often been based on manipulation of silicon, silicon dioxide, and aluminum (Al). Considering the limitations of these materials, new ones are being developed to enhance product performance and reliability.

As oxides grow thinner, reliability assurance engineers need to understand the time dependent dielectric breakdown (TDDB) phenomena. As gate-oxide thickness approaches monolayer dimensions, TDDB studies focus on atomic-level defects. Defects in gate-oxides are not considered "thin spots," but rather the chemical state of the silicon and oxide atoms in the dielectric. The issue of quasi-breakdown--gates or capacitors that become leaky but do not become shorted--is important. As these issues develop, the value of voltage and current ramp tests used for gate-oxide studies is limited. Oxides with quasi-breakdown conditions can show sub-picoamp levels of leakage, and the defect density required for reasonable yield and low infant mortality defects will drop.

The ability to characterize oxides at low fields is critical as oxides become more sensitive to smaller defects. Small-area defects pull relatively little current before they become hard shorts, making them difficult to detect in large test capacitors.

Assuming a defect will increase the electric field by 150% in one small part of the gate oxide, then the current density drawn by that defect under specified test conditions can be calculated. If we further assume a large area for this defect--maybe 10% of the total area of a typical transistor--then the Fowler Nordheim equation can be used to calculate the total current drawn by this defect. Using the equation, the total current drawn will only be 7.6 fA at 3 V. If the total test capacitor's area is 0.1 [cm.sup.2], then the trap-assisted tunneling current in the defect will be 1 pA/[cm.sup.2] or 100 fA. Defects like this are clearly the root cause of gate-oxide failure, but low-tunneling currents make the defects invisible when tested in large capacitors.

The use of an array of smaller test capacitors with the same total area as a single large capacitor makes it possible to detect low-tunneling currents while maintaining a short test time. This does not, however, address the issue of the changing nature of gate-oxide defects.

Characterizing small-area capacitors makes it possible to determine the inherent characteristics of the oxide. Anomalous point defects can be detected and characterized by testing large arrays of these capacitors. The small size of the defects means that the instrumentation must provide femtoamp-level current resolution.

The parasitic capacitance of the interconnect lines takes a dominant role in determining the maximum speed of a semiconductor device. At the same time, the interlevel dielectric's impact on device reliability has increased. Speed degradation is also dependent on changes in the interlevel dielectric.

Ions and dipoles in a dielectric material can diffuse when exposed to an electric field. This movement of charged particles causes a displacement current in the parasitic interconnect capacitors and a change in interconnect capacitance.

New instrumentation, such as the S630 parametric test system from Keithley Instruments Inc., Cleveland, uses a remote picoammeter front-end, per-pin design and an advanced probe card to achieve low levels of parasitic dielectric absorption.

Low-K dielectric materials can show a drift in the measured dielectric constant (K) as a function of time and temperature. This can affect the speed of the product, causing the device to fail. The rate of the chemical reaction that causes this degradation in K can be accelerated by high temperatures.

High-temperature aging of a wafer is difficult due to issues with thermal expansion of the probe and hot chuck. However, high temperatures can be developed within small test structures using self-heating techniques. Current is forced through the poly resistor, resulting in joule heating of the poly line. The temperature of the metal lines is measured using the serpentine metal line on the lower edge of the poly heater. The change in resistance divided by the TCR (thermal coefficient of resistance) for the metal provides the temperature of the metal lines. The current through the heater resistor is ramped up until the metal resistor shows a change in resistance equivalent to the desired stress temperature (typically 450 to 500 [degrees] C). The capacitor is aged for 30 to 120 sec, then allowed to cool back to room temperature. The small thermal mass allows it to be heated to 500 [degrees] C in less than 1 sec and to cool in less than 5 sec.

The amount of current required to drive a self-heated resistor is typically between 150 and 200 mA. Measuring the change in temperature requires instrumentation able to measure a change in resistance of the TCR of the metal--the TCR of copper (Cu) is 0.36%/[degrees] C, so the instrumentation must be able to resolve a 0.36% change in resistance. This measurement is complicated by the fact that the metal line usually has low resistance and the current that is forced through it must be less than that which will cause joule heating.

The size of the capacitor is limited by the fact that the current that can be forced through one probe needle is limited. While multiple probe pads could be connected to one self-heated resistor, this increases the silicon area required to make this measurement.

To reduce the parasitic RC delay associated with the metal interconnect lines, the industry has moved away from traditional Al interconnect metal lines in favor of Cu-based metallization. Copper diffuses easily into Si[O.sub.2] at normal processing temperatures, increasing the metal resistivity and decreasing the isolation between adjacent metal lines. To prevent this, most Cu processes add a refractory barrier metal layer. Thick barrier layers can result in metal line resistance that is higher than A1 lines. Therefore, the thickness of the barrier layer must be minimized. At the same time, cracks or holes in the barrier layer will allow the Cu to diffuse into the adjacent dielectric material and may cause leakage issues.

Initial results of electromigration testing on Cu metal lines indicate that the rate of change of the resistance of the Cu metal line under an electromigration stress will be about one-tenth the rate of change of a similarly stressed A1 line. Therefore, Cu is believed to be less sensitive to electromigration failure than Al lines. However, in the damascene process, the Cu is electroplated into refractory metal line trenches and the surface metal is removed by a chemical mechanical planarization process, leaving metal only in the trenches. The remaining metal is coated with a thin silicon nitride layer.

Early testing of Cu electromigration has reported a significant rate of failure due to adjacent shorts. The results can be confounded by the thermal expansion of the metal at high-stress temperatures and by the fact that the ultimate stress generated in a metal line is a function of the stress current density. Therefore, highly accelerated electromigration tests can result in pessimistic predictions of interlevel oxide failures. The possibility does exist for electromigration stress-induced failure of the sidewall dielectric. Declining mechanical strength associated with some low-K dielectric materials may increase the frequency of such fractures.

The strength of the sidewall oxide can be tested quickly using joule heating. The thermal expansion coefficient of Cu is 16.2 ppm/[degrees] C and Si[O.sub.2] is close to 0.3 ppm/[degrees] C. Heating the line by forcing a high current through it causes it to expand and produces tensile stress in the surrounding oxide layers. The temperature of a line can be measured by the change in resistance of that line. The stress generated by the heating of the line can be calculated from the dimensions and the temperature change. A fast current ramp with a consistent measure of the line resistance/temperature, accompanied by the ability to detect leakage to an adjacent metal line, can be used to measure the strength of the sidewall dielectric.

The instrument required to perform this test must be able to supply a significant current density in the line and measure voltage with a resolution of at least 1 mV.


Defect Density Affects Yield for Different Technologies (Assume 0.2 defects/[cm.sup.2] of gate area and 0.002 defects/m of perimeter)
                            Gate area
              Number of     ([cm.sup.2])   Gate perimeter

Technology    transistors   (total/die)    (m)(total/die)

1.2[micro]     500.0K          0.027          5.1
0.8[micro]       1.5M          0.036         10.2
0.5[micro]       4.5M          0.056         28.35
0.35[micro]     10.0M          0.065         37.8
0.25[micro]     15M            0.10         100.0
0.18[micro]     30.0M          0.13         143.0
0.13[micro]     54.0M          0.19         360.0
0.1[micro]      91.0M          0.25         608.0

Technology    yield (%)

1.2[micro]       98.5
0.8[micro]       97.6
0.5[micro]       94.2
0.35[micro]      92.3
0.25[micro]      78.0
0.18[micro]      69.4
0.13[micro]      24.2
0.1[micro]        0.8

Source: Keithley Instruments Inc.

Turner is director of structures engineering at Keithley Instruments Inc, Cleveland.
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Comment:New Materials Prompt New Reliability Issues.
Author:Turner, Tim
Publication:R & D
Geographic Code:1USA
Date:Dec 1, 2000
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