Printer Friendly

New Developments in Flip Chip.

A recent study, Flip Chip Markets and Infrastructure Developments, by TechSearch International, Inc. (Austin, TX), investigates the growing market for flip chip ICs and the infrastructure that makes the technology possible. Flip chip has expanded in two major areas: 1) the high-performance needs of the microprocessor, the application specific integrated circuit (ASIC) and the high-end digital signal processor (DSP) device and 2) form factor-die sizes are small and packaging cost must be minimized. New to flip chip technology is the expansion into the interconnect realm previously dominated by wire bond. Expansion into mid-range pin counts represents a shift in the adoption of the technology, which is reflected in cost reductions.

Also new is the introduction of wafer- level packages (WLPs). Many low pin count devices (2 to 50 I/Os) are marketed as WLPs-die that are packaged at the wafer level and do not require underfill for thermal stress management. Many WLPs are fabricated using virtually the same bumping process used for conventional flip chip bumped die. While this low pin count application represents millions of die, few wafers are required because thousands of parts can be produced on a single wafer.

For many companies, the key to the expanded use of flip chip has been the availability of low-cost wafer bumping. Prices from service providers have declined and many merchant bumping operations have introduced or have R&D activities for lead-free bumping methods. Products using lead-free bumps have been also been introduced.

More than 20 companies offer flip chip bonders-each suited for a particular application. New underfill materials, with shorter cure times and improved properties, have been introduced; and developments, such as no-flow and reworkable materials, are promising. For more information on the report, visit

Copyright [copyright] 2001 CMP Media LLC
COPYRIGHT 2001 UP Media Group, Inc.
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2001, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

Article Details
Printer friendly Cite/link Email Feedback
Publication:Circuits Assembly
Article Type:Brief Article
Geographic Code:1USA
Date:Sep 1, 2001
Previous Article:Deadline for Ending Halon Use Approaches.
Next Article:PWB and Flex Circuit Production Up.

Related Articles
Flip Chip 2001 Conference; IMAPS Europe Announced.
2001 Semiconductor Packaging and Assembly Outlook.
Flip Chip Bonder.
Flip chip packaging: a hot topic: flip chip technology appears to be one bright spot in the electronics industry after a difficult year.
Flip chip processing factors: implementing flip-chip process capability is not a simple task. Find out how to make the process less painful.
CSP and flip chip assembly using tacky flux: a recent research project found how placement accuracy of CSPs and flip chips is affected by the...
The latest in underfill for advanced chip assembly: is a low-cost, surface-mount-compatible process possible?
Lead-free first-article inspection: typical process concerns associated with LF alloys for first-article OI and line qualification.
A new, thin high-performance organic substrate: the flip-chip package can be conventionally processed and meets lead-free demands.
0.1 cent RFID chip assembly? Technologies to slash manufacturing costs for the ubiquitous tags are being aggressively pursued.

Terms of use | Privacy policy | Copyright © 2021 Farlex, Inc. | Feedback | For webmasters