NEW RULE SETS FOR LEDA CHECKERS ACCELERATE AND DELIVER.
The policy is a source file that is used to configure the LEDA checkers. It contains critical Verilog and VHDL coding-style rules to minimize design flow bottlenecks and optimize quality of results (QoR) for system-on-a-programmable-chip (SOPC) development using Altera programmable logic devices (PLDs) with design-tools such as Synopsys' FPGA Compiler II and FPGA Express.
The Altera coding style policy for LEDA is comprised of a special set of coding-style rules derived from the 300+ rules, pre-packaged with Synopsys' LEDA programmable HDL checker. These rules check for common mistakes and poor design practices such as treatment of module inputs and outputs, resets, inadvertent inference of latches, gating of clocks, etc. Altera determined these rules to be critical for ensuring a smooth design flow and optimum performance when targeting its PLD architectures. Synopsys also worked with Altera to customize error-messages and documentation for these rules, thus giving designers additional guidance for optimizing different tool-execution options and selecting microarchitecture-level component. The Altera Coding Style 1.0 policy will be available December 2000 and can be downloaded free of charge from the Synopsys web site to current LEDA licensees.
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|Title Annotation:||Company Business and Marketing|
|Comment:||NEW RULE SETS FOR LEDA CHECKERS ACCELERATE AND DELIVER.(Company Business and Marketing)|
|Publication:||EDP Weekly's IT Monitor|
|Date:||Oct 30, 2000|
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