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Multilevel inverters with imbricated switching cells, PWM and DPWM-controlled/PWM ir DPWM valdomi daugelio lygmenu inverteriai.


Multilevel voltage inverters with imbricated switching cells are destined to high and very high-power applications. These structures led to the normalization of the voltage distribution when the semiconductor devices are blocked and to the improvement of the total factor of harmonic distortions as compared to the classic inverter structures. Static power converters for high voltages generally need on-off switches (semiconductor devices) that can function under these voltages. If these switches are not available, different converter topologies must be developed, where only a voltage fraction is applied to each switch [1].

Switches connected in series

One of the possible solutions is connecting in series several synchronously-controlled switches [2], in order to obtain a high voltage switch. They must start commutation at the same time, otherwise there may be voltage balance problems, control problems and du/dt stress, generated for each commutation. Fig. 1 presents two circuits illustrating how switches can be connected in series.


It is difficult to realize the static or dynamic balance of voltages on the switches, as it requires special techniques.

--Static balancing can be accomplished by connecting high-value resistances in parallel with every switch;

--Dynamic balancing raises more serious problems.

All switches must commute at the same time. If this condition is not fulfilled, the first switch that becomes blocked (or the one that commutes last) will bear the entire voltage.

In most of the cases, commutations cannot be synchronized by the mere synchronization of control signals. Semiconductor devices must be selected as pairs having the same conduction/blocking time, otherwise we must use special control circuits, capable of compensating the differences between these times [3].

Multilevel voltage inverters with imbricated switching cells

In order to obtain a better distribution of voltage on each switch, new converter structures were developed. The basic structure of a three-level bridge arm is presented in Fig. 2 and is made up of two imbricated switching cells: ([A.sub.1], [B.sub.1]) and ([A.sub.2], [B.sub.2)]. Within each switching cell there are two complementary switches, bidirectional in current and unidirectional in voltage (transistor + diode, connected in antiparallel) [4].

Consequently, this topology solves the problem specific to structures connected in series, namely the static and dynamic balancing of voltages when switches are blocked.


The switches that make up different switching cells can be controlled at different points in time. If the voltage applied on a switch is [U.sub.d]/2 (and assuming the conduction voltage is zero), the voltage supplied by the switching cell ([B.sub.1], [B.sub.2]) can be 0, [U.sub.d]/2 or [U.sub.d] according to the number of switches turned off (0, 1 or 2), which is similar to the classic case of the three-level inverter. In practice, the voltage supply [U.sub.d]/2 must be replaced by a capacitor C charged at [U.sub.d]/2.

In order to determine the voltage steps that can be obtained in the general case, we considered in Fig. 3 that voltages on the capacitors fulfill the following condition:

[] = k[U.sub.d]/n, k = l,...n (1)


The voltage applied to the blocked switch within the switching cell k depends only on the voltage on the capacitor [C.sub.k] and [C.sub.k-1], and is calculated as

[U.sub.OFFk] = k [U.sub.d]/n - (k-1) [U.sub.d]/n = [U.sub.d]/n. (2)

Knowing that the voltage on a blocked switch is [U.sub.d]/n (and assuming that voltage on the switch in conduction state is zero), one can easily understand how the converter works: the voltage released by a multilevel switching cell ([B.sub.1] [B.sub.2],..., [B.sub.n]), whatever the point in time, is calculated by multiplying the voltage step [U.sub.d]/n by the number of switches blocked. This shows that there are n+1 possible voltage levels: 0, [U.sub.d]/n, 2[U.sub.d]/n,..., [U.sub.d].

Control strategy for the multilevel inverter

The control of multilevel switching cells must fulfill simultaneously two important requirements:

--compatibility with voltage [U.sub.Ck] = k[U.sub.d]/n=const, k=l,...n;

--optimization of the harmonic spectrum.


Each capacitor [C.sub.k] is connected between the pairs of switches k and k+1, Fig. 4.

According to their state, the current through the capacitor can be: -[I.sub.A], 0 or +[I.sub.A] (we assumed [I.sub.A] = [i.sub.a] = const. for the duration of a switching period [T.sub.p]). Thus, the current through the capacitor can be expressed as:

[i.sub.Ck] = ([f.sub.Ck] -[f.sub.Ck+1])[I.sub.A], (3)

where [f.sub.Ck] and[f.sub.Ck+1] stand for the connection functions for [A.sub.k] and [A.sub.k+1] switches and can only have two values: 0 or 1 (according to the state of the switches) [5]. For instance, if [f.sub.Ck] = 1 when the [A.sub.k] switch is off and [f.sub.Ck] = 0 when the [A.sub.k] switch is on.

For multilevel converters, in order to obtain equal conduction durations for all the cells of an arm, it is necessary to use "n " carrier waves dephased by [T.sub.p]/n and, thus, stability for capacitors [C.sub.1], ..., [C.sub.n] is attained.

The power circuit of the three-level inverter with imbricated cells and the control strategy are presented in Fig. 5.


The PWM control strategy adopted for an arm consists in comparing a reference (sinusoidal) wave to two carrier (triangular symmetric) waves dephased by 180[degrees] [6]. These comparisons lead to two connection functions for arm [f.sub.c1] and [f.sub.c2] defined as follows:


The performances of the system presented can be improved (reduced harmonic level, increased efficiency, etc.) if, as part of the command strategy, the sinusoidal reference wave is replaced by a modified sinusoidal wave (discontinuous command techniques DPWM) [7], described in (5)


Fig. 8 presents the control strategy applied to the inverter illustrated in Fig. 5, using the modified sinusoidal wave s1 and its corresponding waveform [v.sub.us1], [v.sub.vs1] [v.sub.ws1] for the given situation [8].


Simulation results

Starting from the study presented and using the simulation environment Pspice, we shall present a compared analysis of the functioning of the two-level three-phase inverter [9]. For the simulation of the inverter in Fig. 5, we used the sinusoidal PWM and DPWM control strategies and we took into account the following values: inductive load R=10[ohm], L=10mH, amplitude modulation index [m.sub.a] = 0.95, carrier wave frequency 50Hz, switching frequency 5kHz, and supply voltage amplitude [U.sub.d] = 310 V. Fig. 7 presents the waveforms of the carrier signals [v.sub.p1], [v.sub.p2], of the sinusoidal modulating signals on 50Hz, [v.sub.u], [v.sub.v], [v.sub.w], and of the control signals on switches [A.sub.1], [A.sub.2], implemented by the transistors of the inverter presented in Fig. 5, using the sinusoidal PWM control strategy.





Figures 8, 9 and 10 present the main waveforms obtained by simulating the functioning of the inverter in Fig. 5, using the sinusoidal PWM control strategy.

Fig. 11 presents the waveforms of the carrier signals [vp.sub.1], [vp.sub.2] of the modified sinusoidal modulating signals on 50Hz, [v.sub.us1], [v.sub.vs1], [v.sub.ws1], and the control signals on switches [A.sub.1], [A.sub.2], implemented by the transistors of the inverter presented in Fig. 5, using the DPWM control strategy.





Figures 12, 13 and 14 present the main waveforms obtained by simulating the functioning of the inverter in Fig. 5, using the DPWM control strategy.


The results of the simulation show that, even though each switch (transistor) is controlled with a switching frequency of 5kHz, the harmonic spectrum of the phase and line voltages does not include harmonics due to the switching around this harmonic. Therefore, we can state that the three-level inverter structure with imbricated switching cells doubles the output switching frequency. This work was supported by CNCSIS-UEFISCU, project number PNII-RU, code 335/2010.

This determines fewer current/torque variations, diminished losses in the motor/converter and allows the use of devices of high voltage, but low switching frequencies. On the one hand, the DPWM control strategy allows the increase of the voltage fundamental due to the reduction of the harmonic amplitude at a double switching frequency and, on the other hand, the waveform of the output voltage approximates the sinusoidal waveform more accurately.

Received 2010 03 11


[1.] Aghion C., Ursaru O. Lucanu M., Three phase motor control using modified reference wave // Electronics and Electrical Engineering.--Kaunas: Tehnologija, 2010. No. 3(99).--P. 35-38.

[2.] Floricau D., Fodor D., Teodorescu R. Using commutation functions in modeling power converters // Symposium Electrotehnica, 1996.--P. 81-86.

[3.] Hava A. M., Kerkeman R. J., Lipo T. A. A high performance generalized discontinuous PWM algorithm // IEEE-APEC Conf. Records.--Atlanta, Giorgia, 1997.--P. 886-896.

[4.] Floricau D. Multi-level voltage source inverters with imbricated commutation cells // Journal E.E.A Electrotehnica, 1997.--No. 44.--P. 30-34.

[5.] Hautier J. P., Guillaud X. Le formalisme et les modeles hybrids applique a des convertisseurs statiques electroniques // RGE, 1995.--No. 1(95), Janvier.--P. 25-33.

[6.] Hava A. M., Kerkeman R. J., Lipo T. A. Simple analytical and graphical tools for carrier based PWM methods // IEEE-PESC Conf.Records.--St. Louis, Missouri, 1997.--P. 1462-1471.

[7.] Hava A. M., Kerkeman R. J., Lipo T. A. Carrier based PWM-VSI overmodulation strategies: Analysis, comparison, and design // IEEE Trans. On Power Electronics, 1998.--P. 674-689.

[8.] Meynard T. A., Foch H. Multi-level conversion: High voltage application and voltage source inverters // Proceedings PESC, 1992. P. 397-403.

[9.] Ursaru O., Aghion C., Lucanu M., Hysteretic-controlled Voltage Regulator using Integrated Circuit LM723 // Electronics and Electrical Engineering.--Kaunas: Tehnologija, 2009.--No. 7(95).--P. 45-50.

O. Ursaru, C. Aghion

Technical University "Gheorghe Asachi" of Iasi, Blvd Carol 1, No. 11, Romania, phone: +400232270021/285, e-mails:,
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Author:Ursaru, O.; Aghion, C.
Publication:Elektronika ir Elektrotechnika
Article Type:Report
Geographic Code:4EXRO
Date:Oct 1, 2010
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