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Multiharmonic load termination effects on GaAs MESFET power amplifiers.

Power amplifiers utilized in transmitters of wireless communications products operate at relatively low battery voltages and demand ever increasing amplifier efficiency to provide operability over extended time periods. For example, in portable cellular telephone systems, the power amplifier consumes a significant portion of the total DC current budget, thereby placing a premium on amplifier efficiency. In addition, the size and weight of these products is continually being reduced. This reduction is achieved by decreasing the number of battery cells, which in turn lowers the operating voltage available to the power amplifier. This trend toward lower operating voltages inherently leads to lower amplifier efficiency due to higher losses associated with the transistor and more complex load matching networks required at the transistor output. Given a required RF output power level, any decrease in supply voltage requires a corresponding increase in current, a larger transistor and an output load network with a higher conductance load line. While the higher conductance load line can be achieved by a network providing a larger impedance transformation (impedance scaling), the RF losses associated with this network are higher unless the Q of the individual components can also be increased. Similarly, the Q of the harmonic terminations must also increase if the same efficiency is to be obtained.

Many of today's wireless products, including the domestic analog cellular system, are based on FM schemes where the modulated RF waveform exhibits a constant amplitude envelope. Since the transmitted information is contained only by the frequency/phase content and not by the amplitude of the waveform, the MESFET device can be operated further into gain compression, typically several dB, to obtain better efficiency. Considering that the bandwidth of these systems is generally less than five percent, single-ended topologies operating in a class A/B mode (approximately 10 percent [I.sub.DSS]) with tuned load networks have found wide acceptance.

The performance merits and design requirements for various classes of power amplifiers have been addressed. The necessary design constraints, such as the load terminating conditions needed to achieve that class of operation, are often derived through analytical methods based largely on the device's static IV description. Ideal matching conditions often are assumed, such as all harmonic voltages are terminated with a short circuit at the intrinsic FET drain terminal. In addition, the MESFET device is idealized to some extent, for example, a prescribed transconductance profile that is constant or linear with unilateral gain, to simplify the analysis greatly.(1) While such analytical techniques give valuable insight into the operation of the amplifier and device, the performance sensitivity and dependence on the output load terminations, as well as other MESFET device characteristics are not provided. Further insight can be gained using SPICE and harmonic balance techniques.

This paper investigates load terminations connected to the drain terminal of a GaAs MESFET and their effects on output power, gain and efficiency when the device is biased and terminated in a condition representing a tuned class A/B RF power amplifier. The effect of load terminations at the second, third, fourth and fifth harmonic frequencies is evaluated through the use of a harmonic balance simulator and a large-signal GaAs MESFET model. Predictions from the large-signal model are compared to measured MESFET power characteristics obtained from an on-wafer load pull system to establish model validity. Good agreement is achieved between model predictions and measured data for several measured load terminations. Given confidence in the large-signal model, an extensive number of harmonic balance simulations are performed where the load reflection coefficients at the first four harmonic frequencies are varied independently. From these simulations, gain and efficiency performance contours are constructed. The results show strong correlation between gain and efficiency with the second harmonic termination. Weaker, but still significant correlation is noted for higher order terms.

The effect of losses in harmonic load terminations is also considered for small and larger gate width MESFET devices. The larger device is represented by scaling the basic large-signal MESFET model by a factor of 10 to represent a larger device. Simulations are performed that contrast matching network losses or the equivalent quality factor (Q) with gain, output power and efficiency. As expected, such losses are more dominant with increased device size and load line conductance.

DEVICE CHARACTERIZATION

This study selected a 0.7 [[micro]meter] gate length by 600 [[micro]meter] gate width GaAs MESFET as the basis for extracting a large-signal model. The device was characterized using an on-wafer measurement system to establish a data set from which large-signal model parameters can be extracted. Device characterization and model extraction are based on previous work.(2-4) Characterization consisted of measuring forward-biased S-parameters on the device to determine parasitic resistances [R.sub.s], [R.sub.d] and [R.sub.g]. Similarly, from forward DC IV measurements, ideality factor N and saturation current [I.sub.s] were obtained. S-parameters and DC drain current were measured at numerous values of gate-source [V.sub.gs] and drain-source [V.sub.ds] voltages extending over much of the device's IV plane. At each bias state, FET-equivalent circuit elements ([g.sub.m], [g.sub.ds], [C.sub.gs], [C.sub.gd], [Tau] and [C.sub.ds]) were extracted from the S-parameter measurements.

LARGE-SIGNAL MODEL EXTRACTION

A model extraction algorithm is utilized that determines large-signal model parameter values based on the RF parameter data set of [g.sub.m], [g.sub.ds], [Tau], [C.sub.gs], [C.sub.gd], [C.sub.ds] and DC drain current. A modified Curtice model is selected based on earlier work.(5) This model is implemented in the harmonic balance simulator via user-developed C code routines. Also, gate-source and gate-drain capacitances are modeled with simple diode junction expressions. Drain-source capacitance [C.sub.ds] is assumed to be constant and bias independent.

LARGE-SIGNAL MODEL VALIDATION

Prior to beginning an extensive simulation effort, the accuracy of the large-signal model is compared to power measurements obtained with on-wafer load pull measurements. Measured load pull data consisting of output power and power-added efficiency (PAE) are measured at three unique device terminations listed in Table 1. Measurements are obtained with the device biased at 3.5 V ([V.sub.ds]) and at a drain current of approximately five percent [I.sub.dss]. Load states are chosen such that the device operates with dynamic load lines ranging from shallow to steep conductance. The dynamic load lines predicted by the model for each of the three load states ranging from shallow to steep conductance are shown in Figure 1. PAE is defined as

[P.sub.OUT] - [P.sub.IN]/[P.sub.DC] x 100%

where

[P.sub.IN] = available power from the RF source

[P.sub.OUT] = power delivered to load resistor [R.sub.L] at the fundamental frequency [f.sub.o]

[P.sub.DC] = DC component, [I.sub.dd] [V.sub.dd]
TABLE I
MESFET OUTPUT TERMINATIONS


LOAD LINE                 A                B                C


[[Gamma].sub.Lfo]


mag                  0.216             0.044             0.21
angle               -3.4 [degrees]   137.9 [degrees]   174
[degrees]


Figure 2 compares the agreement between large-signal model predictions (from harmonic balance simulations) of output power and PAE to measured load pull data for each load termination. For all cases, the model predicts output power to within 0.5 dB of the measured value. Similarly, PAE is predicted to within three percent of the measurements. Even closer agreement to the measured data is observed when the device is operated in or near gain compression, as would be the situation for the type of amplifiers considered. During the load pull measurements, the load pull system determined the load reflection coefficients at the fundamental, second, third, fourth and fifth harmonic frequencies for each of the three terminations. These data are used in the harmonic balance simulator to ensure that the actual measurement setup is described adequately. Within the harmonic balance simulator, scattering parameter blocks are constructed that exhibit the same frequency response (impedance up to the fifth harmonic frequency) as the source and load tuners used in the actual load pull measurement system. In this manner, the actual measurement conditions, that is, the impedance terminations presented at the FET gate and drain terminals, are closely duplicated within the harmonic balance simulator, allowing a controlled means of comparing model predictions to measured validation data.

SECOND AND THIRD HARMONIC TERMINATIONS

The effects of multiharmonic terminations are investigated through [TABULAR DATA FOR TABLE II OMITTED] the use of a harmonic balance simulator along with the large-signal model for a 0.7 x 600 [[micro]meter] GaAs MESFET. A block diagram of the circuit used in the simulations is shown in Figure 3. The device is biased quiescently at 3 V ([V.sub.ds]) and at a drain current of approximately 10 percent [I.sub.dss]. In these simulations, S-parameter blocks are used to represent input and output matching networks. One S-parameter block is connected between the RF source and gate terminal that is representative of an input matching network. Values for these S-parameters are determined from simulations such that good power transfer from the RF source to the gate terminal of the device is achieved at the fundamental frequency. This network is reciprocal and lossless (no resistive losses) at the fundamental frequency, and therefore, represents an ideal matching network. At all harmonic frequencies, the input reflection coefficient presented at the gate terminal of the device is set to zero, an ideal 50 [ohms] termination.

Similarly, a two-port S-parameter network is connected between the drain terminal and load resistor [R.sub.L]. At the fundamental frequency of operation, a 50 + j0 ohm load line is presented to the device. At the second and third harmonic frequencies, the magnitude of the reflection coefficient is set to one while the angles [[Theta].sub.L2fo] and [[Theta].sub.L3fo] are allowed to vary independently from 0 to 2[Pi], which represents an ideal lossless terminating network at 2[f.sub.o] and 3[f.sub.o]. Higher order reflection coefficient terms (at the fourth and fifth harmonic frequencies) are set to zero (50 [ohms]). Source and load reflection coefficients are listed in Table 2.

A sinusoidal RF source set at 900 MHz with +4 dBm available power is used in the simulations. This input power level is chosen such that the device operates at approximately 1.5 dB of gain compression when the MESFET is terminated in a purely resistive load network of 50 + j0 ohms, that is, for a load impedance of 50 + j0 ohms at [f.sub.o], 2[f.sub.o], 3[f.sub.o], 4[f.sub.o] and 5[f.sub.o]. A large number of harmonic balance simulations are performed to identify the effect of the second- and third-order harmonic load terminations. The angles of the second harmonic load reflection coefficient ([[Theta].sub.L2fo]) and third harmonic load reflection coefficient ([[Theta].sub.L3fo]) are each varied independently in 6 [degrees] increments, resulting in 3600 simulations. Data were collected from each simulation. Figures 4 and 5 show the developed performance contour plots, indicating the dependence of output power and efficiency on [[Theta].sub.L2fo] and [[Theta].sub.L3fo]. The independent variable, either power or efficiency, is plotted against the angle of the two reflection coefficients [[Theta].sub.L2fo] and [[Theta].sub.L3fo] with all other load terminations [TABULAR DATA FOR TABLE III OMITTED] held fixed. For the PAE contour plot, each contour line represents constant efficiency. These results suggest a strong dependence of efficiency with the second harmonic termination. Best efficiency is obtained at a 2[f.sub.o] short-circuit condition that is representative of a class F-type amplifier. At the other extreme, where [[Theta].sub.L2fo] is at zero degrees (open circuit impedance condition), the efficiency drops by 30 percent. Dependence is also noted with the third harmonic termination, although it appears to be much weaker. Efficiency contours are observed that exhibit small gradients for angles of [[Theta].sub.L2fo] near [Pi]. This performance suggests that for a GaAs MESFET amplifier with the device terminated at the drain terminal with a reflection coefficient of [[Theta].sub.L2fo] near [Pi], high amplifier efficiency can be obtained over a wide range of [[Theta].sub.L3fo] angles.

Similar characteristics are shown for output power. With the available input power from the RF source held constant, the output power and transducer gain exhibit a significant dependence on [[Theta].sub.2fo]. The largest output power, and thus minimum gain compression, are observed at angles of [[Theta].sub.L2fo] near [Theta], which is also coincident with highest efficiency. A much weaker dependence is noted with [[Theta].sub.L3fo]. Since the available power from the RF source is held constant, the gain contours indicate the device operates into differing amounts of gain compression due to [[Theta].sub.L2fo] and [[Theta].sub.L3fo]. For this case, gain compression values ranging from 1 to 4 dB are observed.

FOURTH AND FIFTH HARMONIC TERMINATIONS

The effects of the fourth and fifth harmonic terminations applied to the drain terminal of a 0.7 x 600 [[micro]meter] GaAs MESFET are investigated in a manner similar to the second and third harmonic termination simulations. Based on these simulations, [[Theta].sub.L2fo] is set to an angle of [Pi], while [[Theta].sub.L3fo] is set to an angle of zero. Source and load reflection coefficients are listed in Table 3. The input RF source is maintained at the same power level, frequency and bias as in the second and third harmonic termination simulations.

For efficiency and output power, some dependence is noted with the-fourth harmonic termination while weak dependence is observed with the fifth harmonic. Differences in output power of 0.15 dB are noted. The efficiency also varies by approximately 2.5 percent. The efficiency and output results are shown in Figures 6 and 7, respectively.

RESISTIVE LOSSES IN HARMONIC TERMINATIONS

In previous work, the magnitude of second and third harmonic reflection coefficients has been constrained to unity, which is an ideal lossless termination. However, a practical network realization of these terminations using passive elements will result in a reflection coefficient magnitude of less than one due to losses inherent in the passive components. Since the previous results show strongest dependence with the second harmonic termination, the effects of losses in harmonic terminations will he considered for only second harmonic terminations with all higher order terms fixed and constrained.

In addition, the effect of such loss on larger gate width devices will be considered based on the described large-signal GaAs MESFET model. Two cases with gate width peripheries differing by 10 times will be considered. These models include a 0.6 mm gate width device terminated in a fundamental impedance of 50 + j0 ohms and a 6 mm gate width device terminated in a fundamental impedance of 5 + j0 ohms. The original large-signal model is used to model the smaller device since it was based on measurements of a 0.6 mm gate width device. To represent a 6 mm gate width device, large-signal model parameters are scaled by a factor of 10, that is, capacitance parameters [C.sub.ds], [C.sub.gs], [C.sub.gd] and beta are scaled up 10 times while resistance parameters [R.sub.g], [R.sub.d] and [R.sub.s] are scaled down 10 times. Scaling large-signal model parameters in this manner to describe a larger gate width device may not adequately represent particular physical attributes, such as the distributed effects of larger gate and drain feed networks. Nevertheless, this approach will show qualitative effects in larger devices due to losses in the output matching network.

[TABULAR DATA FOR TABLE IV OMITTED]

Harmonic balance simulations are performed by varying the magnitude of only the second harmonic termination at the MESFET drain terminal for both 0.6 mm and 6 mm gate width devices. The source reflection coefficient and all other load reflection coefficients are held constant. For the 6 mm gate width MESFET device model, source and load reflection coefficients at the harmonic frequencies are derived by impedance scaling from the 0.6 mm device. The available input power level is set to +14 dBm (a 10 dB increase to account for device scaling). Fundamental and harmonic terminations are listed in Table 4.

Results from the harmonic balance simulations are shown in Figure 8. Resistive loss in the second harmonic termination ([absolute value of [[Gamma].sub.L]] at 2[f.sub.o]) significantly influences both output and efficiency. This result is expected since it causes the device to operate with a load line from resistive to tuned[1] (that is, the second harmonic signal is terminated from a resistance to a reactance). The 6 mm device shows a more pronounced drop in efficiency and output power with resistance compared to the 0.6 mm device, thus showing network losses to be more significant in larger devices with higher load line conductances. However, when the [R.sub.L] of the 6 mm device is normalized to the 0.6 mm device, efficiency and output power results are identical, as shown in Figure 9.

CONCLUSION

The effect of load terminations applied to the drain terminal of a GaAs MESFET at the second, third, fourth and fifth harmonic frequencies has been investigated. Results show a strong dependence in efficiency and output power with the second harmonic termination and weaker correlation to higher harmonic terms. In addition, resistive losses in the second harmonic termination may limit performance, especially in higher power designs employing steeper conductance load lines.

References

1. L.J. Kushner, "Microwave Power Amplifier Analysis and Design," Technical Report 16, Massachusetts Institute of Technology Lincoln Laboratory, December, 1988.

2. Microwave MESFETs and HEMTs, J. Michael Golio, ed., Artech House, Norwood, MA, 1991.

3. J. Costa, M. Miller, M. Golio and G. Norris, "Fast, Accurate, On-wafer Extraction of Parasitic Resistances and Inductances in GaAs MESFETs and HEMTs," 1992 MTT-S International Symposium Digest, June 1992, pp. 1011-1014.

4. GASMAP User's Manual, Artech House, Norwood, MA, 1991.

5. J. Staudinger, et al., "Considerations for Improving the Accuracy of Large-signal GaAs MESFET Models to Predict Power Amplifier Performance," IEEE Journal of Solid-State Circuits," March 1994, pp. 366-373.
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Author:Staudinger, Joe
Publication:Microwave Journal
Date:Apr 1, 1996
Words:3013
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