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Method for generating DC-DC converters with required characteristics.

1 INTRODUCTION

The main part of any electronic device and/or electric vehicle is its power supply. In recent year, DC-DC Converters are the power parts in the major of many electronic or electric devices (Computers, Embedded Systems, etc). However, the development and minimization of these converters do not happen at the same speed as digital parts of these devices. This is because the design (generation and development) of the DC-DC converter is based only on the skills and experience of the designer (Mitchell, 1988; Erickson, 2004), unlike in digital parts that have several mathematical and algorithmic methods for their implementations and simplifications (Calcutta et al., 2004). There are a lot of the new designed DC-DC converters which their implementation and topology are presented in (Su and Peng, 2005; Dudrik and Oetter, 2007; Rajarajeswari and Thanushkodi, 2008;. Kelley et al.2005; James et al., May 2009; lee et al., January 2010). The different loads require different features and characteristics of DC-DC converters. The common trends for all DC-DC converters are: high efficiency, increasing the switching frequencies for reducing the total size and weight, improved power density and dynamic performance, etc.

There are different series of designed DC-DC converters, but their design based only on the skills of the designers. There are no fully algorithmic methods that can be translated into computer program for designing and generating these power electronic converter circuits.

This work proposes algorithmic method that can be translated into computer program for generating and implementing sub-families of DC-DC converters with predetermined features.

Main Topological Matrix "MTM": Definition & Features

Any electrical circuit with a number of b elements can be represented by graph (Artemenko and Taher, 1994; Deo, 2004; Diestel, 2005; Taher, July 2011), containing b- branches and n- nodes. By the graph theory branches are divided into two topological groups: bT- tree branches and bL-links. A tree of the graph is a subset of the branches such that all graph nodes are connected by branches but without forming a closed path (bT = n - 1). Then these branches are the tree branches. The remaining branches (collectively called a co-tree bL) are the links (bL = b - bT = b - n + 1). Given a network graph with b branches and n nodes select a tree, we can obtain the Matrix of Independent Meshes MIM (KVL loop equations), and Matrix of Independent Nodes MIN (KCL equations). There are b-(n - 1) independent KVL equations and n - 1 independent KCL equations.

Definition of MTM

For the topological relations between MIM and MIN, we will consider basic step-up/step- down converter shown in Fig.1. In Fig.2 the graph for this circuit is shown, in which the bold lines show tree branches [b.sub.T] and dashed lines show the links [b.sub.L]. Matrix of Independent Meshes and Matrix Independent Nodes MIM and MIN are shown in Fig3 and Fig.4 respectively. For the undirected graph, MIM and MIN are matching (Matrix transportations) and can be combined as shown in Fig.5, a.

[FIGURE 1 OMITTED]

[FIGURE 2 OMITTED]

[FIGURE 5 OMITTED]

The Fig.5a shows the Matrix of Independent Meshes MIM (KVL equations)- for the horizontal view (rows) and Matrix of Independent Nodes MIN (KCL equations)- for the vertical view (columns). Unity sub-matrixes in the left side and in the down of Fig.5a can be removed and we will obtain the Matrix that we named the Main Topological Matrix "MTM" as shown in Fig.5,b. This MTM will be the tool for generating converter circuits;" MTM will be used for generating converter circuits" (backward using MTM).

Features and descriptions of MTM

Now, we will formulate the general features and characteristics of MTM matrix that will be used for formulation of the logical equations for the syntheses of our converters:

* Equality (identity) of MTM 's columns satisfies the corresponding elements in the series (E in series with S- see Fig.5);

* Equality (identity) of MTM's row satisfies the corresponding elements in parallel. Also the existence unity one in the row of MTM satisfies the corresponding elements of branch and link are linked in parallel (G in parallel with C--see Fig.5);

* Any other meshes (dependent mesh) can be obtained from logical addition (logical operation--X OR) two or more MTM's rows.

* Any other nodes (dependent node) can be obtained from logical addition (logical operation XOR) two or more MTM's columns.

* Isomorphic circuits have identical MTM. This means we have also a tool for the identification of isomorphism (This problem is called: subgraph isomorphism problem-isomorphic circuits have identical MTM)

* The MTM Matrix will be designated by m, and its cells by m[i,j] or mi,j, and m[i,j] element [euro] {0,1}: 1- element is present (exists) in the corresponding mesh or node, 0- means the corresponding element is absent from the corresponding mesh or node (also we can designate it as [m.sub.i,j]).

* There are Column and Row matrixes for the MTM. For example in Fig.5, column C = [0 1 1] means m[1,2] = 0, m[2,2] = 1, and m[3,2] = 1. Column matrix E = m[1 1 0] means m[1,3] = m[2,3] = 1 and m[3,3] = 0. Row Matrix L = [1 0 1] it means: m[1,1] = m[1,3] = 1, and m[1,2] = 0. Row Matrix G = [0 1 0] means m[3,1] = m[3,3] = 0, and m[3,2] = 1. The sign [conjunction] will designate the logical XOR operation.

Formulating the Common Principles of DC-DC Converters: Operation and their Design Approach by Using MTM

The common operation principles for all DC-DC Converters (Single-Switch Switched Mode Power Supply SMPS) are the two timing intervals; some switches are "ON" in the first timing interval and others are "OFF". In the second timing interval will be vice versa. This means the switches that were "ON" in first interval will be "OFF" in the second timing interval and the switches that were "OFF" in first interval will be "ON" in the second timing interval (we can distinguish two equivalent circuits). S -designates the switch that will be "ON" in the first timing interval (S-type switch). The number of S-type switches is designated by s. V -will designate the switch that will be "ON" in the second timing interval (V-type switch) and their number will be designated by v.

For Single-Switch DC-DC Converters the number of Capacitors (c) should equal the number of inductive elements (l): c = l and this parameter will be designated by q.

For Single-Switch DC-DC Converter's graph, the number of the independent meshes [9] is k = l+ v+ 1 - (1 corresponding the load resistance) in the first timing interval of operation, and the number of independent meshes is k = l+ s+ 1 in the second timing interval of operation. Since the graph contains a fixed number of independent meshes, so v = s (number of S-type switches should be equal to the number of V- type switches). And this parameter will be designated by p.

From the above the number of the Independent Meshes KVL equation for the graph circuits for Single-Switch DCDC Converters: k = q+ p+1, and the number of the independent nodes (KCL equations) u = b- k, where b- is the number of circuit's elements.

We will follow the following approaches for all DC-DC Converters:

* Neglecting the losses in all the components of DC-DC converter--All switches, coils, transformers (multi-winding coils) are assumed ideal elements.

* S--type switch--the switches that transfer energy from DC source ( switches that absorb energy from the energy source, these switches are "ON" in the first interval of the operation),

* V-type switch--the switches that delivered the energy which stored in magnetic elements to the load.

* E--Input Voltage Source.

* L1, L2, Ll--Inductive elements (transformers, single or multi-winding coils)

* C1, C2, Cc--Capacitors.

* The load resistance R = 1/G--assumed in parallel with output capacitor(s) won't be shown in MTM.

* Element MTM m[i.j] of our converter will satisfy: i [less than or equal to] k, and J [less than or equal to] u.

Generating Subclasses of Single-Switch DC-DC Converters by Using MTM

* Subclass DC-DC Converters with two switches (demonstration example)

Generating subclass DC-DC converters with two switches (s = v = 1), and two reactive elements (one Inductive element L and one output Capacitor C: c = l = 1) will be as the following:

The structure of MTM for these subclass converters are shown in Fig.6, the inductive element L- assumes a single-winding coil. From the above discussion the number of the independent Meshes is k = p + q + 1 = 3. As the links of the graph we will choose the elements L, V, and G. The remaining elements S, C, and E will be the tree branches. Since the load G conductance is always in parallel with the output capacitor C, it can be unconsidered (removed) in the MTM in this phase (generating phase procedure).

[FIGURE 8 OMITTED]

Now we will write the logical equations that determine the completion of MTM for generating these sub-class converters:

* m [1, 1] = m [1, 3] = 1 -First timing interval (Energy is absorbed from E i.e. forming the loop ELS.., ..., this equation can be rewritten: m11 AND m12 = 1)

* m[1,1] [conjunction] m[2,1] = 0--Second timing interval (forming the loop LV ...,that not contents the switch S which will be "off" in this timing interval)

* m[2,1] = 1--from the above Equation.

* m12 [conjunction] m22 = 1--Condition to be the loop LV ... contains the capacitor C (forming the loop LVC ...). The sign [conjunction] is the XOR logical operation

* C [conjunction] E [not equal to] 0--Column Matrix C = [m[1,2] m [2,2]] and Column Matrix E = [[1,3] [2,3]] should be different if not so then C and E will be in series and the equivalent circuit will be as shown in Fig.8. In this case the output voltage will be equal to the input, or the output voltage will be zero. This connection should be eliminated Taking into account the logical equations above the MTM will be completed and the alternatives of Column Matrixes C and E of MTM (with decimal codes) will be as the following:

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII]

And by this way we get all alternatives of MTMs. Therefore, we obtained the three alternative circuits familiar as the basic DC-DC converters as shown in Fig.9, a, b, c with their MTM "The load G- is always connected in parallel with the output capacitor C"

[FIGURE 9 OMITTED]

Using MTM for Generating DC-DC Converters with Galvanic Isolation

In the majority of applications, it is required to incorporate a transformer (multi-winding inductor) into the switching converter, to obtain dc isolation between the converter input and output. However, since transformer (multi-winding inductor) size and weight vary inversely with frequency. This transformer operates at the converter switching frequency of tens or hundreds of kilohertz. These high frequencies lead to dramatic reductions in transformer size and weight (modern ferrite power transformers is much minimized). In addition some applications are required the converters with high output voltage.

* Generating Subclass Converter with Four Switches and Four Reactive Elements

The MTM structure of these Subclass converters with high output voltage and Galvanic Isolation: converters with 4 Switches (q = 2) and four reactive elements (p = 2) is shown in Fig. 10. In Fig.10a is shown the MTM structure of the converters in witch galvanic isolation GI is accomplished by one multi-winding inductor- L2. And the Fig.10b shows the MTM structure of the converters that galvanic isolation is accomplished by two multi-winding inductors- L1 and L2. This GI (Galvanic Isolation) attribute is reflected (encoded) by zero Sub-matrixes in our MTM as shown in the Fig.13.

For accomplishing the high output voltage the input current could be continuously, so the section (super node) of the input E with one or two inductors should be exist in this converters: this feature will be encoded in the logical equations for MTM. In addition the tow capacitors will be in the output part of converters to be accomplished voltage multiplication in the output: also this feature will be encoded in the following logical equations. As in the previous examples the electrical Load not shown in this phase: in the design phase. And the load will be in parallel with output capacitor/s.

[x] Sub-class converters that galvanic isolation GI is accomplished by one multi-winding inductor:

The logical equations for the MTM in Fig.10a- converters in witch the galvanic isolation GI is accomplished by one multi-winding inductor are:

* m11 = m12 = 1--Condition for energy absorbing from E (forming the loop ESL.., this equation can be rewritten: m11 AND m12 = 1)

* = m43 = m45 = 1--Condition for energy delivered to the output (forming the loop V2L2C2 ...)

* m31 = m41 = m32 = m14 = m24 = m 15 = m25 = 0--The condition for GI

* m21 = m22 = 1--To be accomplished that E and L1 will be in series (condition for continuous input current and high voltage at the output)

* m33 = 1--To remove the series connection C1 and C2

* m13 [conjunction] m23 = 1--To be accomplished different values for m13 and m23: to remove the parallel connection S1 and V1.

Taking into account the logical equations above the alternatives two combinations of MTMs can be obtained as shown in Fig.10a. And the sub-class of this DC-DC converter circuits is shown in the Fig.11a, b (two different converters a and b).

[FIGURE 11 OMITTED]

[FIGURE 12 OMITTED]

[x] Sub-class converters that galvanic isolation GI is accomplished by two multi-winding inductor:

The logical equation for the MTM in Fig.10b: converters in witch the galvanic isolation GI is accomplished by two multi-winding inductor L1 and L2:

* m11 = m12 = 1--Condition for energy absorbing from E (forming the loop ESL.., this equation can be rewritten: m11 AND m12 = 1)

* = m43 = m45 = 1--Condition for energy delivered to the output (forming the loop V2L2C2 ...) as in the above

* m31 = m41 = m32 = m14 = m24 = m 15 = m25 = 0--The condition for GI

* E [conjunction] L1 [conjunction] L2 = 0--for forming the node with E,L1, and L2 (condition for continuous input current and high voltage at the output)

* m32 = m33 = m42 = 1 and m13 = 0--from the above equation

* m22 [conjunction] m23 = 1: To remove the parallel connection S1 and V1.

Considering the logical equations above the alternatives two combinations of MTMs can be obtained as shown in Fig.10b. And the sub-class of this DCDC converter circuits is shown in the Fig.12a, b (two converter circuits a and b).

Algorithm and Software Implementation

In the Fig.13 is shown the proposed flowchart for generating MTMs of subfamily of the converters that satisfies required features. These features are encoded in the logical equations. The functions of the software are:

[check] Receive the parameters of the converters p and q to determinate the dimension of MTM.

[check] Generate all possible combinations of MTM's matrixes.

[check] Print all possible topological MTM's combination matrixes that satisfies the logical equations for the determined sub-class of the circuits.

The software is beginning to receive the parameters p and q, generate all possible combinations of binary numbers to MTM (Countv--count variable incremented from ... 0000 to ... 1111). The mask variable (mask_v) each time is shifted left so we can complete each cells in the MTM by 0 or 1. Next each completed MTM has to be checked for satisfying the logical equations, if so the software will print the MTM (the topological matrix of the circuit). These procedures are repeated until all combinations will be finished.

[FIGURE 13 OMITTED]

Conclusion

This paper develops and proposes a fully algorithmic method for synthesizing and generating DC--DC converters by using MTM. By using the topological matrix MTM we generate all sub-class circuits of the DC-DC converters with predetermined characteristics. These predetermined characteristics for converters are encoded (implied) in the logical equations of the designed circuits. So we can call this method--the design by parts for synthesizing and generating converter circuits with predetermined characteristics

Isomorphic circuits have identical MTM, so we have also a tool for identification of isomorphism of the circuits.

This method can be developed for synthesizing and designing not only DCDC converters, but also another electronic circuits like filters circuits ... etc. And the proposed algorithm can be translated to computer program for synthesis different classes of power electronic circuits. This method gives ability to cooperative design and the ability to build library of logical equations and/or classes for different power electronic circuits.

References

Mitchell, D.M. (1988). DC-DC Switching Regulator Analysis. USA, McGraw-Hill Book Company.

Erickson, R.W. (2004). Fundamentals of Power Electronics. Cluwer Academic Publishers.

Calcutta, D., Cowan, F., Parchizadeh, H. (2004). 8051 Microcontrollers--An Applications Based System Introduction. Newnes, Linacre House, Jordan Hill, Oxford OX2 8DP

Su, G.J., Peng, F.Z.G. J. (2005). A Low Cost, Triple-Voltage Bus DC-DC Converter for Automotive Applications. The IEEE Applied Power Electronics Conference and Exposition (APEC), vol. 2, pp. 1015-1021, March 6-10, Austin, Texas.

Dudrik, J., Oetter, J. (2007). High-Frequency Soft-Switching DC-DC Converters for Voltage and Current DC Power Sources. Acta Polytechnic Hungarian, Vol. 4, No. 2.pp.29-46. Hungary.

Rajarajeswari, N., Thanushkodi K. (2008). Design of an Intelligent Bi-Directional DC-DC Converter with Half Bridge Topology. Euro Journals Publishing, ISSN 1450-216X Vol.22 No.1 (2008), pp.90-97.

Kelley, R., Mazola, M., Draper, W., Cassidy, J. (2005). Inherently Safe DC-DC Converter Using a Normally-On SiC JFET. In Proc. of IEEE APEC, pp.1561-1565.

James, P., Forsyth, A., Calderon-Lopez, G., Pickert, V. (2009, May). DC-DC converter for hybrid and all electric vehicles. EVS24 University of Manchester, UK.

Jong-pil lee, Byung-duk min, Tae-jin kim, Dong-wook yoo and Ji-yoon yoo (2010, Janury). Input-Series-Output-Parallel Connected DC/DC Converter for a Photovoltaic PCS with High Efficiency under a Wide Load Range. Journal of Power Electronics, Vol. 10, No. 1, pp. 9-13.

Artemenko, M.E., Taher, M.A. (1994). Synthesis transistor's Converters with determined characteristics. Technical Electrodynamics,, Kiev, N4, pp. 43-47.

.Deo, N. (2004). Graph Theory with Applications to Engineering and Computer Science. PHL learning Prt, ltd.

Diestel, R. (2005). Graph theory, Third Edition. Springer--Berlin. Taher, M.A (2011, July).

ALGORITHMIC METHOD FOR GENERATING DC-DC CONVERTER CIRCUITS BY USING TOPOLOGICAL MATRIX. International conference DEIS 2011 London, UK, Communications in Computer and Information Science (CCIS), Vol. 194, pp. 714- 723.

Murad Ahmed Ali Taher

Assistant Professor Hodeidah University, Yemen Department of Computer Engineering

dr_muradabsi@yahoo.com
Fig 3: The MIM matrix of the converter.

L   V   G   S   C    E

1           1        1
    1       1   -1   1
        1       -1

Fig 4: The MIN matrix of the converter.

L   V    G   S   C   E

1   -1       1
    1    1       1
1   -1               1

Fig.6: Structure of MTM
for basic DC-DC Converters.

    S   C   E

L   x   x   x   1
V   x   x   x   2

Fig. 7: Possible MTM's for basic
converters (see text).

    S   C   E

L   1   x   1   1
V   1   x   x   2

    1   2   3

Fig. 10: Structure of MTM for Converters
with 4 switches and 4 reactive element

a): GI by One L

           In     GI        Out

           E    L1   L2   C1    C2

In    S1   1    1    0     0    0
      V1   1    1    1     0    0

Out   S2   0    0    1     1    0
      V2   0    0    1    1/0   1

b): GI by two L

           In     GI        Out

           E    L1   L2   C1    C2

In    S1   1    1    0     0    0
      V1   1    0    1     0    0
Out   S2   0    1    1     1    0
      V2   0    1    1    1/0   1
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Author:Taher, Murad Ahmed Ali
Publication:International Journal of New Computer Architectures and Their Applications
Article Type:Report
Date:Jan 1, 2012
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